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| author | Shawn Lin <shawn.lin@rock-chips.com> | 2016-11-16 16:49:23 +0800 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2016-11-16 12:37:37 +0100 |
| commit | e44dde27949254b7da7259ab90864c211c14ade3 (patch) | |
| tree | 8dba2fb525c2cf4f75abed81c7b0fe71b067ea3f /drivers/clk/rockchip/clk.h | |
| parent | aac343ebb35e3428cf3b101cc16f8aa082817b37 (diff) | |
| download | op-kernel-dev-e44dde27949254b7da7259ab90864c211c14ade3.zip op-kernel-dev-e44dde27949254b7da7259ab90864c211c14ade3.tar.gz | |
clk: rockchip: add clock controller for rk1108
Add the clock tree definition and driver for rk1108 SoC.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Tested-by: Jacob Chen <jacob2.chen@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip/clk.h')
| -rw-r--r-- | drivers/clk/rockchip/clk.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 1653edd..d67eecc 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -34,6 +34,21 @@ struct clk; #define HIWORD_UPDATE(val, mask, shift) \ ((val) << (shift) | (mask) << ((shift) + 16)) +/* register positions shared by RK1108, RK2928, RK3036, RK3066, RK3188 and RK3228 */ +#define RK1108_PLL_CON(x) ((x) * 0x4) +#define RK1108_CLKSEL_CON(x) ((x) * 0x4 + 0x60) +#define RK1108_CLKGATE_CON(x) ((x) * 0x4 + 0x120) +#define RK1108_SOFTRST_CON(x) ((x) * 0x4 + 0x180) +#define RK1108_GLB_SRST_FST 0x1c0 +#define RK1108_GLB_SRST_SND 0x1c4 +#define RK1108_MISC_CON 0x1cc +#define RK1108_SDMMC_CON0 0x1d8 +#define RK1108_SDMMC_CON1 0x1dc +#define RK1108_SDIO_CON0 0x1e0 +#define RK1108_SDIO_CON1 0x1e4 +#define RK1108_EMMC_CON0 0x1e8 +#define RK1108_EMMC_CON1 0x1ec + #define RK2928_PLL_CON(x) ((x) * 0x4) #define RK2928_MODE_CON 0x40 #define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44) |
