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| author | Michael Turquette <mturquette@linaro.org> | 2014-11-28 21:00:16 -0800 |
|---|---|---|
| committer | Michael Turquette <mturquette@linaro.org> | 2014-11-28 21:00:16 -0800 |
| commit | b572b5f821abb350439609f367bd35961f53a28e (patch) | |
| tree | 380542ae6d32a0f32763062af3194d9628560123 /drivers/clk/rockchip/clk.c | |
| parent | 250d07d1e782e68e9b2e7b637703b3739f0ec1b1 (diff) | |
| parent | 89bf26cbc1a09476c4c4740d16a0ffdfa2192b9c (diff) | |
| download | op-kernel-dev-b572b5f821abb350439609f367bd35961f53a28e.zip op-kernel-dev-b572b5f821abb350439609f367bd35961f53a28e.tar.gz | |
Merge tag 'v3.19-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
- clock phase setting capability for the rk3288 mmc clocks
- pll init to allow syncing to actual rate table values
- some more exported clocks
- fixes for some clocks (typos etc) all of them not yet used
in actual drivers
Diffstat (limited to 'drivers/clk/rockchip/clk.c')
| -rw-r--r-- | drivers/clk/rockchip/clk.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index 70559fa..20e05bb 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -197,7 +197,8 @@ void __init rockchip_clk_register_plls(struct rockchip_pll_clock *list, list->parent_names, list->num_parents, reg_base, list->con_offset, grf_lock_offset, list->lock_shift, list->mode_offset, - list->mode_shift, list->rate_table, &clk_lock); + list->mode_shift, list->rate_table, + list->pll_flags, &clk_lock); if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s\n", __func__, list->name); @@ -268,6 +269,14 @@ void __init rockchip_clk_register_branches( list->gate_offset, list->gate_shift, list->gate_flags, flags, &clk_lock); break; + case branch_mmc: + clk = rockchip_clk_register_mmc( + list->name, + list->parent_names, list->num_parents, + reg_base + list->muxdiv_offset, + list->div_shift + ); + break; } /* none of the cases above matched */ |
