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| author | Heiko Stuebner <heiko@sntech.de> | 2015-06-20 16:06:02 +0200 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2016-02-04 15:54:20 +0100 |
| commit | 36714529f8bbd4f8eaf93b50f4a64c52a24879aa (patch) | |
| tree | 5dfef90e5569cd0ad8f90cf2eac5ca58525eb94f /drivers/clk/rockchip/clk-rk3188.c | |
| parent | 29a30c269aba4223e2a8b443f443d7def1e43fea (diff) | |
| download | op-kernel-dev-36714529f8bbd4f8eaf93b50f4a64c52a24879aa.zip op-kernel-dev-36714529f8bbd4f8eaf93b50f4a64c52a24879aa.tar.gz | |
clk: rockchip: convert manually created factor clocks to the new type
Clean up the init code and move the creation of factor clocks to the
appropriate positions coming from the clock architecture diagrams.
This also unifies the artificial separation of the hclk_vcodec etc clocks
again.
We do keep the separate definition of some watchdog and usb480m pseudo
clocks for now, as they're not real factor clocks from the clock-tree
but placeholders for fixes to come (usb480m gets supplied by the
missing driver for the new usbphy type and the watchdog-gate is sitting
somewhere else together which we cannot model currently).
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip/clk-rk3188.c')
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3188.c | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c index 629c65d..40bab39 100644 --- a/drivers/clk/rockchip/clk-rk3188.c +++ b/drivers/clk/rockchip/clk-rk3188.c @@ -339,6 +339,8 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { INVERTER(0, "pclk_cif0", "pclkin_cif0", RK2928_CLKSEL_CON(30), 8, IFLAGS), + FACTOR(0, "xin12m", "xin24m", 0, 1, 2), + /* * the 480m are generated inside the usb block from these clocks, * but they are also a source for the hsicphy clock. @@ -754,7 +756,6 @@ static const char *const rk3188_critical_clocks[] __initconst = { static void __init rk3188_common_clk_init(struct device_node *np) { void __iomem *reg_base; - struct clk *clk; reg_base = of_iomap(np, 0); if (!reg_base) { @@ -764,12 +765,6 @@ static void __init rk3188_common_clk_init(struct device_node *np) rockchip_clk_init(np, reg_base, CLK_NR_CLKS); - /* xin12m is created by an cru-internal divider */ - clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2); - if (IS_ERR(clk)) - pr_warn("%s: could not register clock xin12m: %ld\n", - __func__, PTR_ERR(clk)); - rockchip_clk_register_branches(common_clk_branches, ARRAY_SIZE(common_clk_branches)); |
