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| author | Julien CHAUVEAU <julien.chauveau@neo-technologies.fr> | 2014-11-21 11:08:47 +0100 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2014-11-23 01:55:14 +0100 |
| commit | 12c0a0e81e2f9c03404a3e095517c022991aad43 (patch) | |
| tree | 33305edb4c4b0b41169216e012066443f4d99420 /drivers/clk/rockchip/clk-pll.c | |
| parent | b7bdb7f45e7b848dc2eb50c2d5c5106af68562c4 (diff) | |
| download | op-kernel-dev-12c0a0e81e2f9c03404a3e095517c022991aad43.zip op-kernel-dev-12c0a0e81e2f9c03404a3e095517c022991aad43.tar.gz | |
clk: rockchip: fix rk3188 USB HSIC PHY clock divider
The USB HSIC PHY clock divider is set in the register RK2928_CLKSEL_CON(11).
Signed-off-by: Julien CHAUVEAU <julien.chauveau@neo-technologies.fr>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip/clk-pll.c')
0 files changed, 0 insertions, 0 deletions
