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authorGeert Uytterhoeven <geert+renesas@glider.be>2016-06-27 16:51:14 +0200
committerGeert Uytterhoeven <geert+renesas@glider.be>2016-08-09 09:53:47 +0200
commitb51d5275016c6edbf4656eaee30d836fef127016 (patch)
treecf8c1fb3ef2b4ad4e8e944b5b582b1c31cb135f7 /drivers/clk/renesas
parent2570d4005d475818711c96e83fb84d5048ab8e1b (diff)
downloadop-kernel-dev-b51d5275016c6edbf4656eaee30d836fef127016.zip
op-kernel-dev-b51d5275016c6edbf4656eaee30d836fef127016.tar.gz
clk: renesas: r8a7796: Add watchdog module clock
Add the module clock for the Watchdog Timer (WDT) controller on the Renesas R-Car M3-W (r8a7796) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas')
-rw-r--r--drivers/clk/renesas/r8a7796-cpg-mssr.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index ea9ed38..c0dee76 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -104,6 +104,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
DEF_MOD("scif2", 310, R8A7796_CLK_S3D4),
+ DEF_MOD("rwdt0", 402, R8A7796_CLK_R),
DEF_MOD("intc-ap", 408, R8A7796_CLK_S3D1),
};
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