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| author | Srinivas Kandagatla <srinivas.kandagatla@linaro.org> | 2016-02-22 11:43:39 +0000 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2016-02-22 14:15:53 -0800 |
| commit | 732d6913691848db9fabaa6a25b4d6fad10ddccf (patch) | |
| tree | 709e8daa51429f280679614510cffa4dd4b8013a /drivers/clk/qcom | |
| parent | f073cd8a3e7b3b7d5f572b8178aa4abe6115e52f (diff) | |
| download | op-kernel-dev-732d6913691848db9fabaa6a25b4d6fad10ddccf.zip op-kernel-dev-732d6913691848db9fabaa6a25b4d6fad10ddccf.tar.gz | |
clk: qcom: msm8960: fix ce3_core clk enable register
This patch corrects the enable register offset which is actually 0x36cc
instead of 0x36c4
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Fixes: 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/qcom')
| -rw-r--r-- | drivers/clk/qcom/gcc-msm8960.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c index 983dd7d..63ecd97 100644 --- a/drivers/clk/qcom/gcc-msm8960.c +++ b/drivers/clk/qcom/gcc-msm8960.c @@ -2769,7 +2769,7 @@ static struct clk_branch ce3_core_clk = { .halt_reg = 0x2fdc, .halt_bit = 5, .clkr = { - .enable_reg = 0x36c4, + .enable_reg = 0x36cc, .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "ce3_core_clk", |
