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| author | Stephen Boyd <sboyd@codeaurora.org> | 2015-04-09 23:02:02 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2015-09-16 15:22:18 -0700 |
| commit | 8ee9c7de019596445fd81e7647f5509d90e2fb72 (patch) | |
| tree | f877edf0cbedbcb87f87a30ca1de822630a2c579 /drivers/clk/qcom/clk-rcg.h | |
| parent | db544f1b583aadc818b00ff528eb1744b3bbcac6 (diff) | |
| download | op-kernel-dev-8ee9c7de019596445fd81e7647f5509d90e2fb72.zip op-kernel-dev-8ee9c7de019596445fd81e7647f5509d90e2fb72.tar.gz | |
clk: qcom: Allow clk_set_parent() to work on display clocks
Sometimes the display driver may want to change the parent PLL of
the display clocks (byte and pixel clocks) depending on the
use-case. Currently the parent is fixed by means of having a
frequency table with one entry that chooses a particular parent.
Remove this restriction and use the parent the clock is
configured for in the hardware during clk_set_rate(). This
requires consumers to rely on the default parent or to configure
the parent with clk_set_parent()/assigned-clock-parents on the
clocks before calling clk_set_rate().
Tested-by: Archit Taneja <architt@codeaurora.org>
Cc: Hai Li <hali@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/qcom/clk-rcg.h')
| -rw-r--r-- | drivers/clk/qcom/clk-rcg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h index 56028bb..31f92d7 100644 --- a/drivers/clk/qcom/clk-rcg.h +++ b/drivers/clk/qcom/clk-rcg.h @@ -171,6 +171,7 @@ struct clk_rcg2 { extern const struct clk_ops clk_rcg2_ops; extern const struct clk_ops clk_edp_pixel_ops; extern const struct clk_ops clk_byte_ops; +extern const struct clk_ops clk_byte2_ops; extern const struct clk_ops clk_pixel_ops; #endif |
