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| author | Thierry Reding <treding@nvidia.com> | 2015-04-20 15:13:36 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2016-04-28 12:41:50 +0200 |
| commit | a91bb605ec5f93676e503267c89469d02c5b4cbc (patch) | |
| tree | 1f692e3aa61cd951112d17416c3a86570ddbbac0 /drivers/clk/clk-twl6040.c | |
| parent | eede7113aabd3f40f8d9c32b1690f2859fcb101a (diff) | |
| download | op-kernel-dev-a91bb605ec5f93676e503267c89469d02c5b4cbc.zip op-kernel-dev-a91bb605ec5f93676e503267c89469d02c5b4cbc.tar.gz | |
clk: tegra: Add sor_safe clock
The sor_safe clock is a fixed factor (1:17) clock derived from pll_p. It
has a gate bit in the peripheral clock registers. While the SOR is being
powered up, sor_safe can be used as the source until the SOR brick can
generate its own clock.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/clk-twl6040.c')
0 files changed, 0 insertions, 0 deletions
