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| author | George Cherian <george.cherian@ti.com> | 2014-05-02 12:02:03 +0530 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2014-05-05 13:18:50 -0400 |
| commit | f9786f419d58fc6667ba07a5590640112b31ba64 (patch) | |
| tree | b9aae203f04a1a47dba68073f590424e1c60c4f9 /drivers/clk/at91 | |
| parent | 09c5537246fd469625d116080ab1caa72d170d96 (diff) | |
| download | op-kernel-dev-f9786f419d58fc6667ba07a5590640112b31ba64.zip op-kernel-dev-f9786f419d58fc6667ba07a5590640112b31ba64.tar.gz | |
ARM: AM43xx: clk: Change the cpts ref clock source to dpll_core_m5 clk
cpsw_cpts_rft_clk has got the choice of 3 clocksources
-dpll_core_m4_ck
-dpll_core_m5_ck
-dpll_disp_m2_ck
By default dpll_core_m4_ck is selected, witn this as clock
source the CPTS doesnot work properly. It gives clockcheck errors
while running PTP.
clockcheck: clock jumped backward or running slower than expected!
By selecting dpll_core_m5_ck as the clocksource fixes this issue.
In AM335x dpll_core_m5_ck is the default clocksource.
Signed-off-by: George Cherian <george.cherian@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/clk/at91')
0 files changed, 0 insertions, 0 deletions
