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authorZhenyu Wang <zhenyuw@linux.intel.com>2010-11-02 17:30:46 +0800
committerChris Wilson <chris@chris-wilson.co.uk>2010-11-04 09:39:50 +0000
commit16a02cf08a2de0863daf7ebb91718d7c6bbe7f9c (patch)
tree8a4d083794272b7d7bf82aad75076a7722164b23 /drivers/char
parent8d0f56708292ca5c256ee3b7187d124afee81d93 (diff)
downloadop-kernel-dev-16a02cf08a2de0863daf7ebb91718d7c6bbe7f9c.zip
op-kernel-dev-16a02cf08a2de0863daf7ebb91718d7c6bbe7f9c.tar.gz
agp/intel: fix cache control for sandybridge
This is broken from 97ef1bdd0bc75bce7b2058e9c432b6c277dcf4d3. Let's set the correct bit for LLC+MLC and LLC only. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/char')
-rw-r--r--drivers/char/agp/intel-gtt.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 791216d..9272c38 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1213,11 +1213,11 @@ static void gen6_write_entry(dma_addr_t addr, unsigned int entry,
if (type_mask == AGP_USER_MEMORY)
pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;
else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) {
- pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;
+ pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID;
if (gfdt)
pte_flags |= GEN6_PTE_GFDT;
} else { /* set 'normal'/'cached' to LLC by default */
- pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID;
+ pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;
if (gfdt)
pte_flags |= GEN6_PTE_GFDT;
}
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