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authorChris Wilson <chris@chris-wilson.co.uk>2012-09-14 11:57:47 +0100
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-09-20 14:23:07 +0200
commitedef7e685da05c13cce50c0126189c80fe2c8f71 (patch)
tree75e463e8ffee14669477a56ce366280fc76d16e4 /drivers/char
parent934d6086ea6b165af9218e8dcc2a9e69e1850743 (diff)
downloadop-kernel-dev-edef7e685da05c13cce50c0126189c80fe2c8f71.zip
op-kernel-dev-edef7e685da05c13cce50c0126189c80fe2c8f71.tar.gz
agp/intel: Use a write-combining map for updating PTEs
Rewriting the PTE entries using an WC mapping is roughly an order of magnitude faster than through the uncached mapping. This makes an observable difference on workloads that cycle through large numbers of buffers, for example Chromium using ShmPixmaps where virtually all the CPU time is currently spent rebinding the userptr. v2: Limit the WC mapping to older generations as we have observed that the TLB invalidation on SandyBridge+ is unreliable with WC updates. See i-g-t/tests/gem_gtt_cpu_tlb Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/char')
-rw-r--r--drivers/char/agp/intel-gtt.c11
1 files changed, 8 insertions, 3 deletions
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 7fa655a..e01f5ea 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -666,9 +666,14 @@ static int intel_gtt_init(void)
gtt_map_size = intel_private.base.gtt_total_entries * 4;
- intel_private.gtt = ioremap(intel_private.gtt_bus_addr,
- gtt_map_size);
- if (!intel_private.gtt) {
+ intel_private.gtt = NULL;
+ if (INTEL_GTT_GEN < 6)
+ intel_private.gtt = ioremap_wc(intel_private.gtt_bus_addr,
+ gtt_map_size);
+ if (intel_private.gtt == NULL)
+ intel_private.gtt = ioremap(intel_private.gtt_bus_addr,
+ gtt_map_size);
+ if (intel_private.gtt == NULL) {
intel_private.driver->cleanup();
iounmap(intel_private.registers);
return -ENOMEM;
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