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authorJesse Barnes <jbarnes@virtuousgeek.org>2012-03-28 13:39:33 -0700
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-03-29 00:02:25 +0200
commit4b60d29ee00cb2114075e8b5c2c23928bbd76c28 (patch)
tree67d587028223587f89ab78f5f098a033d4cf482c /drivers/char/agp
parent90b107c8f7ea75ef55db4e0515dda86b245f8978 (diff)
downloadop-kernel-dev-4b60d29ee00cb2114075e8b5c2c23928bbd76c28.zip
op-kernel-dev-4b60d29ee00cb2114075e8b5c2c23928bbd76c28.tar.gz
agp/intel: map more registers for use by the GTT code
We need to flush the Gunit TLB when we update GTT PTEs on VLV, but the register for doing so is above the range we normally map. Map the whole register space to make sure we can get it. v2: only map the larger space on gen7+ (Daniel) Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/char/agp')
-rw-r--r--drivers/char/agp/intel-gtt.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 5cf47ac..269cb02 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1206,12 +1206,16 @@ static inline int needs_idle_maps(void)
static int i9xx_setup(void)
{
u32 reg_addr;
+ int size = KB(512);
pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &reg_addr);
reg_addr &= 0xfff80000;
- intel_private.registers = ioremap(reg_addr, 128 * 4096);
+ if (INTEL_GTT_GEN >= 7)
+ size = MB(2);
+
+ intel_private.registers = ioremap(reg_addr, size);
if (!intel_private.registers)
return -ENOMEM;
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