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| author | Zhenyu Wang <zhenyuw@linux.intel.com> | 2010-07-09 10:45:17 -0700 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2010-08-01 19:03:48 -0700 |
| commit | a2757b6fab6dee3dbf43bdb7d7226d03747fbdb1 (patch) | |
| tree | f3f30e2921f93fc6bfbcf0a8a13fba872b40de3e /drivers/char/agp/intel-agp.h | |
| parent | 3869d4a8afd3ce97770e66d6a96672af93984cc2 (diff) | |
| download | op-kernel-dev-a2757b6fab6dee3dbf43bdb7d7226d03747fbdb1.zip op-kernel-dev-a2757b6fab6dee3dbf43bdb7d7226d03747fbdb1.tar.gz | |
agp/intel: Add actual definitions of the Sandybridge PTE caching bits.
Diffstat (limited to 'drivers/char/agp/intel-agp.h')
| -rw-r--r-- | drivers/char/agp/intel-agp.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h index 2547465..c05e3e5 100644 --- a/drivers/char/agp/intel-agp.h +++ b/drivers/char/agp/intel-agp.h @@ -60,6 +60,12 @@ #define I810_PTE_LOCAL 0x00000002 #define I810_PTE_VALID 0x00000001 #define I830_PTE_SYSTEM_CACHED 0x00000006 +/* GT PTE cache control fields */ +#define GEN6_PTE_UNCACHED 0x00000002 +#define GEN6_PTE_LLC 0x00000004 +#define GEN6_PTE_LLC_MLC 0x00000006 +#define GEN6_PTE_GFDT 0x00000008 + #define I810_SMRAM_MISCC 0x70 #define I810_GFX_MEM_WIN_SIZE 0x00010000 #define I810_GFX_MEM_WIN_32M 0x00010000 |
