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authorJeff Garzik <jeff@garzik.org>2007-09-27 07:41:50 -0400
committerJens Axboe <axboe@carl.home.kernel.dk>2007-10-10 09:25:59 +0200
commit4e953a216265f8646360fa909bdc87ea4bf446b3 (patch)
tree7ee287e00404496b221f69664dad6d2169c3fdf1 /drivers/block/umem.h
parentee4a7b6874469244ed0e3b8fde20028e0bb52642 (diff)
downloadop-kernel-dev-4e953a216265f8646360fa909bdc87ea4bf446b3.zip
op-kernel-dev-4e953a216265f8646360fa909bdc87ea4bf446b3.tar.gz
drivers/block/umem: trim trailing whitespace
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/block/umem.h')
-rw-r--r--drivers/block/umem.h14
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/block/umem.h b/drivers/block/umem.h
index 3a3819a..375c689 100644
--- a/drivers/block/umem.h
+++ b/drivers/block/umem.h
@@ -87,13 +87,13 @@
#define DMASCR_DMA_COMPLETE 0x40000
#define DMASCR_CHAIN_COMPLETE 0x80000
-/*
-3.SOME PCs HAVE HOST BRIDGES WHICH APPARENTLY DO NOT CORRECTLY HANDLE
-READ-LINE (0xE) OR READ-MULTIPLE (0xC) PCI COMMAND CODES DURING DMA
-TRANSFERS. IN OTHER SYSTEMS THESE COMMAND CODES WILL CAUSE THE HOST BRIDGE
-TO ALLOW LONGER BURSTS DURING DMA READ OPERATIONS. THE UPPER FOUR BITS
-(31..28) OF THE DMA CSR HAVE BEEN MADE PROGRAMMABLE, SO THAT EITHER A 0x6,
-AN 0xE OR A 0xC CAN BE WRITTEN TO THEM TO SET THE COMMAND CODE USED DURING
+/*
+3.SOME PCs HAVE HOST BRIDGES WHICH APPARENTLY DO NOT CORRECTLY HANDLE
+READ-LINE (0xE) OR READ-MULTIPLE (0xC) PCI COMMAND CODES DURING DMA
+TRANSFERS. IN OTHER SYSTEMS THESE COMMAND CODES WILL CAUSE THE HOST BRIDGE
+TO ALLOW LONGER BURSTS DURING DMA READ OPERATIONS. THE UPPER FOUR BITS
+(31..28) OF THE DMA CSR HAVE BEEN MADE PROGRAMMABLE, SO THAT EITHER A 0x6,
+AN 0xE OR A 0xC CAN BE WRITTEN TO THEM TO SET THE COMMAND CODE USED DURING
DMA READ OPERATIONS.
*/
#define DMASCR_READ 0x60000000
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