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authorBartlomiej Zolnierkiewicz <bzolnier@gmail.com>2009-12-03 20:32:10 +0100
committerJeff Garzik <jgarzik@redhat.com>2009-12-03 16:01:13 -0500
commited869ff0c70d482de0dc97c3138ff42cbf87aed5 (patch)
tree700fed51c47eb3dfc8080c42eef50a74db3688b9 /drivers/ata/pata_it8213.c
parent088ccb53a341b5c0afab67e392b053ebb0bf7b2b (diff)
downloadop-kernel-dev-ed869ff0c70d482de0dc97c3138ff42cbf87aed5.zip
op-kernel-dev-ed869ff0c70d482de0dc97c3138ff42cbf87aed5.tar.gz
pata_it8213: fix PIO2 underclocking
[ port of Sergei's fixes for pata_efar from commit 5f33b3b ] Fix the PIO mode 2 using mode 0 timings -- this driver should enable the fast timing bank starting with PIO2, just like the PIIX/ICH drivers do. Also, fix/rephrase some comments while at it. Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat (limited to 'drivers/ata/pata_it8213.c')
-rw-r--r--drivers/ata/pata_it8213.c13
1 files changed, 6 insertions, 7 deletions
diff --git a/drivers/ata/pata_it8213.c b/drivers/ata/pata_it8213.c
index 092af53..f0bf77a 100644
--- a/drivers/ata/pata_it8213.c
+++ b/drivers/ata/pata_it8213.c
@@ -92,18 +92,17 @@ static void it8213_set_piomode (struct ata_port *ap, struct ata_device *adev)
{ 2, 1 },
{ 2, 3 }, };
- if (pio > 2)
- control |= 1; /* TIME1 enable */
+ if (pio > 1)
+ control |= 1; /* TIME */
if (ata_pio_need_iordy(adev)) /* PIO 3/4 require IORDY */
- control |= 2; /* IORDY enable */
+ control |= 2; /* IE */
/* Bit 2 is set for ATAPI on the IT8213 - reverse of ICH/PIIX */
if (adev->class != ATA_DEV_ATA)
- control |= 4;
+ control |= 4; /* PPE */
pci_read_config_word(dev, idetm_port, &idetm_data);
- /* Enable PPE, IE and TIME as appropriate */
-
+ /* Set PPE, IE, and TIME as appropriate */
if (adev->devno == 0) {
idetm_data &= 0xCCF0;
idetm_data |= control;
@@ -122,7 +121,7 @@ static void it8213_set_piomode (struct ata_port *ap, struct ata_device *adev)
pci_write_config_byte(dev, 0x44, slave_data);
}
- idetm_data |= 0x4000; /* Ensure SITRE is enabled */
+ idetm_data |= 0x4000; /* Ensure SITRE is set */
pci_write_config_word(dev, idetm_port, idetm_data);
}
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