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authorCatalin Marinas <catalin.marinas@arm.com>2014-04-03 17:48:54 +0100
committerCatalin Marinas <catalin.marinas@arm.com>2014-05-09 15:47:45 +0100
commita41dc0e841523efe1df7fa5ad48b5e9027a921df (patch)
treec162086a45807902dd8c510132f3c3f82603d3e6 /crypto/rmd320.c
parent89ca3b881987f5a4be4c5dbaa7f0df12bbdde2fd (diff)
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arm64: Implement cache_line_size() based on CTR_EL0.CWG
The hardware provides the maximum cache line size in the system via the CTR_EL0.CWG bits. This patch implements the cache_line_size() function to read such information, together with a sanity check if the statically defined L1_CACHE_BYTES is smaller than the hardware value. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Will Deacon <will.deacon@arm.com>
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