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authorstanley.miao <stanley.miao@windriver.com>2010-08-16 09:21:19 +0300
committerTony Lindgren <tony@atomide.com>2010-08-16 09:21:19 +0300
commit8098bb0d8c7fe4ace7d13274c85a149503eee114 (patch)
tree3d350f5cdb8c6abddfacb9584caafcee2c8694f3 /arch
parent77c0870ca515667b77750b397008d68a17fad9d8 (diff)
downloadop-kernel-dev-8098bb0d8c7fe4ace7d13274c85a149503eee114.zip
op-kernel-dev-8098bb0d8c7fe4ace7d13274c85a149503eee114.tar.gz
OMAP3: Fix a cpu type check problem
cpu_is_omap3517() and cpu_is_omap3505() are the subgroups of cpu_is_omap34xx(), so we should check cpu_is_omap3517() and cpu_is_omap3505() first, then check cpu_is_omap34xx(). Otherwise, All AM35XX (Sitara) clocks do not get registered and device drivers (ti_hecc, etc...) that depend on those clocks are failing to get the clock and end up with non working device. Signed-off-by: Stanley.Miao <stanley.miao@windriver.com> Tested-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-omap2/clock3xxx_data.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 138646d..dfdce2d 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3417,7 +3417,13 @@ int __init omap3xxx_clk_init(void)
struct omap_clk *c;
u32 cpu_clkflg = CK_3XXX;
- if (cpu_is_omap34xx()) {
+ if (cpu_is_omap3517()) {
+ cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
+ cpu_clkflg |= CK_3517;
+ } else if (cpu_is_omap3505()) {
+ cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
+ cpu_clkflg |= CK_3505;
+ } else if (cpu_is_omap34xx()) {
cpu_mask = RATE_IN_3XXX;
cpu_clkflg |= CK_343X;
@@ -3432,12 +3438,6 @@ int __init omap3xxx_clk_init(void)
cpu_mask |= RATE_IN_3430ES2PLUS;
cpu_clkflg |= CK_3430ES2;
}
- } else if (cpu_is_omap3517()) {
- cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
- cpu_clkflg |= CK_3517;
- } else if (cpu_is_omap3505()) {
- cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
- cpu_clkflg |= CK_3505;
}
if (omap3_has_192mhz_clk())
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