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| author | Andi Kleen <ak@linux.intel.com> | 2014-08-07 17:08:54 -0700 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2014-08-13 07:51:12 +0200 |
| commit | 03de874aa76ac0adcf6f56ebf3de623d09a5dde3 (patch) | |
| tree | c4190d88c46dea2838ed6e5c4700cdd4b527764b /arch | |
| parent | e708d7ad80737496870fd0b6794704d063fb0cdc (diff) | |
| download | op-kernel-dev-03de874aa76ac0adcf6f56ebf3de623d09a5dde3.zip op-kernel-dev-03de874aa76ac0adcf6f56ebf3de623d09a5dde3.tar.gz | |
perf/x86: Fix :pp without LBR
This fixes a side effect of Kan's earlier patch to probe the LBRs at boot
time. Normally when the LBRs are disabled cycles:pp is disabled too.
So for example cycles:pp doesn't work.
However this is not needed with PEBSv2 and later (Haswell) because
it does not need LBRs to correct the IP-off-by-one.
So add an extra check for PEBSv2 that also allows :pp
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Cc: kan.liang@intel.com
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Link: http://lkml.kernel.org/r/1407456534-15747-1-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/x86/kernel/cpu/perf_event.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c index 2879ecd..0646d3b 100644 --- a/arch/x86/kernel/cpu/perf_event.c +++ b/arch/x86/kernel/cpu/perf_event.c @@ -387,7 +387,7 @@ int x86_pmu_hw_config(struct perf_event *event) precise++; /* Support for IP fixup */ - if (x86_pmu.lbr_nr) + if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2) precise++; } |
