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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2015-03-03 11:58:06 +0100 |
|---|---|---|
| committer | Jiri Kosina <jkosina@suse.cz> | 2015-05-26 15:07:07 +0200 |
| commit | 47b2d14294e04918205950f824fe099505cd4a03 (patch) | |
| tree | 95de4efe20d9d5c23e6c9719f36e73baf6ed0dbf /arch | |
| parent | 0e4f93e5017d9d8080bbd34db17836e090eb46fe (diff) | |
| download | op-kernel-dev-47b2d14294e04918205950f824fe099505cd4a03.zip op-kernel-dev-47b2d14294e04918205950f824fe099505cd4a03.tar.gz | |
ARM: KVM: fix comment
Fix spelling in comment.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/include/asm/kvm_asm.h | 2 | ||||
| -rw-r--r-- | arch/arm64/include/asm/kvm_asm.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/include/asm/kvm_asm.h b/arch/arm/include/asm/kvm_asm.h index 3a67bec..6b9e5a2 100644 --- a/arch/arm/include/asm/kvm_asm.h +++ b/arch/arm/include/asm/kvm_asm.h @@ -23,7 +23,7 @@ #define c0_MPIDR 1 /* MultiProcessor ID Register */ #define c0_CSSELR 2 /* Cache Size Selection Register */ #define c1_SCTLR 3 /* System Control Register */ -#define c1_ACTLR 4 /* Auxilliary Control Register */ +#define c1_ACTLR 4 /* Auxiliary Control Register */ #define c1_CPACR 5 /* Coprocessor Access Control */ #define c2_TTBR0 6 /* Translation Table Base Register 0 */ #define c2_TTBR0_high 7 /* TTBR0 top 32 bits */ diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h index 4838421..7e04f6a 100644 --- a/arch/arm64/include/asm/kvm_asm.h +++ b/arch/arm64/include/asm/kvm_asm.h @@ -27,7 +27,7 @@ #define MPIDR_EL1 1 /* MultiProcessor Affinity Register */ #define CSSELR_EL1 2 /* Cache Size Selection Register */ #define SCTLR_EL1 3 /* System Control Register */ -#define ACTLR_EL1 4 /* Auxilliary Control Register */ +#define ACTLR_EL1 4 /* Auxiliary Control Register */ #define CPACR_EL1 5 /* Coprocessor Access Control */ #define TTBR0_EL1 6 /* Translation Table Base Register 0 */ #define TTBR1_EL1 7 /* Translation Table Base Register 1 */ |
