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| author | Matthew Wilcox <matthew@wil.cx> | 2006-10-10 08:01:20 -0600 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@suse.de> | 2006-12-01 14:36:57 -0800 |
| commit | ebf5a24829def5d066922ceebde61dd57fdc6b1e (patch) | |
| tree | 5df978f750d554f2fd2cdd6f5694be943fd80e9f /arch | |
| parent | 3efe2d84c8d909567c7976a7106114127b8c3470 (diff) | |
| download | op-kernel-dev-ebf5a24829def5d066922ceebde61dd57fdc6b1e.zip op-kernel-dev-ebf5a24829def5d066922ceebde61dd57fdc6b1e.tar.gz | |
PCI: Use pci_generic_prep_mwi on sparc64
The setting of the CACHE_LINE_SIZE register in sparc64's pci
initialisation code isn't quite adequate as the device may have
incompatible requirements. The generic code tests for this, so switch
sparc64 over to using it.
Since sparc64 has different L1 cache line size and PCI cache line size,
it would need to override the generic code like i386 and ia64 do. We
know what the cache line size is at compile time though, so introduce a
new optional constant PCI_CACHE_LINE_BYTES.
Signed-off-by: Matthew Wilcox <matthew@wil.cx>
Signed-off-by: David Miller <davem@davemloft.net>
Acked-by: Jeff Garzik <jeff@garzik.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/sparc64/kernel/pci.c | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/arch/sparc64/kernel/pci.c b/arch/sparc64/kernel/pci.c index e02f01b..dfc41cd 100644 --- a/arch/sparc64/kernel/pci.c +++ b/arch/sparc64/kernel/pci.c @@ -646,13 +646,4 @@ int pci_domain_nr(struct pci_bus *pbus) } EXPORT_SYMBOL(pci_domain_nr); -int pcibios_prep_mwi(struct pci_dev *dev) -{ - /* We set correct PCI_CACHE_LINE_SIZE register values for every - * device probed on this platform. So there is nothing to check - * and this always succeeds. - */ - return 0; -} - #endif /* !(CONFIG_PCI) */ |
