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authorStefan Roese <sr@denx.de>2008-12-05 01:58:49 +0000
committerJosh Boyer <jwboyer@linux.vnet.ibm.com>2008-12-11 10:03:02 -0500
commitcd85400a022335a92fa3c25827179a7ad5e02225 (patch)
tree8190ebc04222bf5a05e5bbc81c07d2d51f1a7616 /arch
parent84d727a109081684c2e01b811cb0d6dc3b9380ca (diff)
downloadop-kernel-dev-cd85400a022335a92fa3c25827179a7ad5e02225.zip
op-kernel-dev-cd85400a022335a92fa3c25827179a7ad5e02225.tar.gz
powerpc/4xx: Add L2 cache node to AMCC Canyonlands dts file
With this patch the L2 cache is enabled on Canyonlands to increase the overall performance. There is a known cache coherency issue with the L2 cache, but this is related to the high bandwidth (HB) PLB segment where the memory address is 0x8.xxxx.xxxx (low bandwidth PLB segment is mapped to 0x0.xxxx.xxxx). Since this HB address is currently unused it is safe to enable the L2 cache. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/boot/dts/canyonlands.dts11
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/canyonlands.dts b/arch/powerpc/boot/dts/canyonlands.dts
index 0c6d318..8b5ba82 100644
--- a/arch/powerpc/boot/dts/canyonlands.dts
+++ b/arch/powerpc/boot/dts/canyonlands.dts
@@ -40,6 +40,7 @@
d-cache-size = <32768>;
dcr-controller;
dcr-access-method = "native";
+ next-level-cache = <&L2C0>;
};
};
@@ -104,6 +105,16 @@
dcr-reg = <0x00c 0x002>;
};
+ L2C0: l2c {
+ compatible = "ibm,l2-cache-460ex", "ibm,l2-cache";
+ dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
+ 0x030 0x008>; /* L2 cache DCR's */
+ cache-line-size = <32>; /* 32 bytes */
+ cache-size = <262144>; /* L2, 256K */
+ interrupt-parent = <&UIC1>;
+ interrupts = <11 1>;
+ };
+
plb {
compatible = "ibm,plb-460ex", "ibm,plb4";
#address-cells = <2>;
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