summaryrefslogtreecommitdiffstats
path: root/arch
diff options
context:
space:
mode:
authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2008-12-18 19:13:46 +0000
committerPaul Mackerras <paulus@samba.org>2008-12-21 14:21:16 +1100
commit760ec0e02d8a13d0ed60d99f47879d4aa8ef1910 (patch)
tree180754d608bad7ba08d9a2f24a4ef930f564a391 /arch
parent2a4aca1144394653269720ffbb5a325a77abd5fa (diff)
downloadop-kernel-dev-760ec0e02d8a13d0ed60d99f47879d4aa8ef1910.zip
op-kernel-dev-760ec0e02d8a13d0ed60d99f47879d4aa8ef1910.tar.gz
powerpc/44x: No need to mask MSR:CE, ME or DE in _tlbil_va on 440
The handlers for Critical, Machine Check or Debug interrupts will save and restore MMUCR nowadays, thus we only need to disable normal interrupts when invalidating TLB entries. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/mm/tlb_nohash_low.S19
1 files changed, 10 insertions, 9 deletions
diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S
index 763c59f..f900a39 100644
--- a/arch/powerpc/mm/tlb_nohash_low.S
+++ b/arch/powerpc/mm/tlb_nohash_low.S
@@ -75,18 +75,19 @@ _GLOBAL(_tlbil_va)
mfspr r5,SPRN_MMUCR
rlwimi r5,r4,0,24,31 /* Set TID */
- /* We have to run the search with interrupts disabled, even critical
- * and debug interrupts (in fact the only critical exceptions we have
- * are debug and machine check). Otherwise an interrupt which causes
- * a TLB miss can clobber the MMUCR between the mtspr and the tlbsx. */
+ /* We have to run the search with interrupts disabled, otherwise
+ * an interrupt which causes a TLB miss can clobber the MMUCR
+ * between the mtspr and the tlbsx.
+ *
+ * Critical and Machine Check interrupts take care of saving
+ * and restoring MMUCR, so only normal interrupts have to be
+ * taken care of.
+ */
mfmsr r4
- lis r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@ha
- addi r6,r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@l
- andc r6,r4,r6
- mtmsr r6
+ wrteei 0
mtspr SPRN_MMUCR,r5
tlbsx. r3, 0, r3
- mtmsr r4
+ wrtee r4
bne 1f
sync
/* There are only 64 TLB entries, so r3 < 64,
OpenPOWER on IntegriCloud