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authorMarkos Chandras <markos.chandras@imgtec.com>2014-07-18 10:51:31 +0100
committerRalf Baechle <ralf@linux-mips.org>2014-09-22 13:35:52 +0200
commit80bc94d10466c710158d5f30c43625ed9fa59e78 (patch)
treed91cca1d045d8fccf6503747459a027114c239b3 /arch
parentfb02035083d9e2de1deba529b45835a698944f07 (diff)
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op-kernel-dev-80bc94d10466c710158d5f30c43625ed9fa59e78.tar.gz
MIPS: pgtable-bits: Define the CCA bit for WC writes on Ingenic cores
Ingenic uses the CCA:1 bit to achieve write-combine memory writes. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7401/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/include/asm/pgtable-bits.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index 011b0dc..e747bfa 100644
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -240,6 +240,11 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */
#define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */
+#elif defined(CONFIG_MACH_JZ4740)
+
+/* Ingenic uses the WA bit to achieve write-combine memory writes */
+#define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT)
+
#endif
#ifndef _CACHE_CACHABLE_NO_WA
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