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authorRanjith Lohithakshan <ranjithl@ti.com>2010-03-31 04:16:30 -0600
committerPaul Walmsley <paul@pwsan.com>2010-03-31 04:16:30 -0600
commitd54a45e2533ef33678dc340298b022a289d2b3e3 (patch)
tree9e112f501b5695b2798dd78d3ec142d8eddfd97d /arch
parent766d305fead341889e7b9611fdc97236075a29fb (diff)
downloadop-kernel-dev-d54a45e2533ef33678dc340298b022a289d2b3e3.zip
op-kernel-dev-d54a45e2533ef33678dc340298b022a289d2b3e3.tar.gz
OMAP3: clock: fix enable bit used for dpll4_m4x2 clock
The enable bit for dpll4_m4x2 clock should be OMAP3430_PWRDN_DSS1_SHIFT. The code erroneously uses OMAP3430_PWRDN_CAM_SHIFT which is meant for dpll4_m5x2 clock. This came into notice during a recent review of the clock tree. Signed-off-by: Ranjith Lohithakshan <ranjithl@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-omap2/clock3xxx_data.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index d5153b6..9cba556 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -895,7 +895,7 @@ static struct clk dpll4_m4x2_ck = {
.ops = &clkops_omap2_dflt_wait,
.parent = &dpll4_m4_ck,
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
- .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
+ .enable_bit = OMAP3430_PWRDN_DSS1_SHIFT,
.flags = INVERT_ENABLE,
.clkdm_name = "dpll4_clkdm",
.recalc = &omap3_clkoutx2_recalc,
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