diff options
| author | Heiko Stuebner <heiko@sntech.de> | 2014-09-13 00:34:29 +0200 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2014-10-20 11:52:24 +0200 |
| commit | be8a77c54815b311485a348547ec80803ee9415b (patch) | |
| tree | 772c123f75d053a75e81f35fe4c87b3b963cfe0d /arch | |
| parent | f114040e3ea6e07372334ade75d1ee0775c355e1 (diff) | |
| download | op-kernel-dev-be8a77c54815b311485a348547ec80803ee9415b.zip op-kernel-dev-be8a77c54815b311485a348547ec80803ee9415b.tar.gz | |
ARM: dts: rockchip: add operating points and armclk references
Add basic OPP entries for current supported Rockchip SoCs.
The operating points are currently very conservative, so individual
boards may opt to redefine them.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/rk3066a.dtsi | 12 | ||||
| -rw-r--r-- | arch/arm/boot/dts/rk3188.dtsi | 15 | ||||
| -rw-r--r-- | arch/arm/boot/dts/rk3288.dtsi | 19 |
3 files changed, 43 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index ad9c2db..8b11fbd5 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -26,11 +26,21 @@ #size-cells = <0>; enable-method = "rockchip,rk3066-smp"; - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x0>; + operating-points = < + /* kHz uV */ + 1008000 1075000 + 816000 1025000 + 600000 1025000 + 504000 1000000 + 312000 975000 + >; + clock-latency = <40000>; + clocks = <&cru ARMCLK>; }; cpu@1 { device_type = "cpu"; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index ddaada7..ae4f049 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -26,11 +26,24 @@ #size-cells = <0>; enable-method = "rockchip,rk3066-smp"; - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x0>; + operating-points = < + /* kHz uV */ + 1608000 1350000 + 1416000 1250000 + 1200000 1150000 + 1008000 1075000 + 816000 975000 + 600000 950000 + 504000 925000 + 312000 875000 + >; + clock-latency = <40000>; + clocks = <&cru ARMCLK>; }; cpu@1 { device_type = "cpu"; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 874e66d..cb18bb4 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -47,10 +47,27 @@ #address-cells = <1>; #size-cells = <0>; - cpu@500 { + cpu0: cpu@500 { device_type = "cpu"; compatible = "arm,cortex-a12"; reg = <0x500>; + operating-points = < + /* KHz uV */ + 1608000 1350000 + 1512000 1300000 + 1416000 1200000 + 1200000 1100000 + 1008000 1050000 + 816000 1000000 + 696000 950000 + 600000 900000 + 408000 900000 + 312000 900000 + 216000 900000 + 126000 900000 + >; + clock-latency = <40000>; + clocks = <&cru ARMCLK>; }; cpu@501 { device_type = "cpu"; |
