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authorKenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>2010-12-01 09:40:32 -0800
committerH. Peter Anvin <hpa@linux.intel.com>2010-12-13 16:52:52 -0800
commit086e8ced65d9bcc4a8e8f1cd39b09640f2883f90 (patch)
tree3d0e6ee303ab0cce2bd3319a5a24bc94c37538eb /arch
parent254e42006c893f45bca48f313536fcba12206418 (diff)
downloadop-kernel-dev-086e8ced65d9bcc4a8e8f1cd39b09640f2883f90.zip
op-kernel-dev-086e8ced65d9bcc4a8e8f1cd39b09640f2883f90.tar.gz
x86, vt-d: Fix the vt-d fault handling irq migration in the x2apic mode
In x2apic mode, we need to set the upper address register of the fault handling interrupt register of the vt-d hardware. Without this irq migration of the vt-d fault handling interrupt is broken. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> LKML-Reference: <1291225233.2648.39.camel@sbsiddha-MOBL3> Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Cc: stable@kernel.org [v2.6.32+] Acked-by: Chris Wright <chrisw@sous-sol.org> Tested-by: Takao Indoh <indou.takao@jp.fujitsu.com> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/x86/kernel/apic/io_apic.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index 226060e..fadcd74 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -3412,6 +3412,7 @@ dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
msg.data |= MSI_DATA_VECTOR(cfg->vector);
msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
msg.address_lo |= MSI_ADDR_DEST_ID(dest);
+ msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest);
dmar_msi_write(irq, &msg);
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