summaryrefslogtreecommitdiffstats
path: root/arch
diff options
context:
space:
mode:
authorBen Dooks <ben-linux@fluff.org>2008-12-12 00:24:19 +0000
committerBen Dooks <ben-linux@fluff.org>2009-03-08 12:37:05 +0000
commitef30e14420df546bc6576b00f9caf3379b6699d1 (patch)
tree8037b6f610fee43c8b71088dd0a6d65d7d6df937 /arch
parent4e59c25dcbc1f033d043f1009a7f6aaa1f2aef26 (diff)
downloadop-kernel-dev-ef30e14420df546bc6576b00f9caf3379b6699d1.zip
op-kernel-dev-ef30e14420df546bc6576b00f9caf3379b6699d1.tar.gz
[ARM] S3C: Rename sleep.S functions to be non-cpu specific
Rename s3c2410_cpu_resume to s3c_cpu_resume and s3c2410_cpu_save to s3c_cpu_save to remove the CPU specific naming of these functions which are now in the generic PM code. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-s3c2410/pm.c2
-rw-r--r--arch/arm/mach-s3c2412/mach-jive.c2
-rw-r--r--arch/arm/plat-s3c/include/plat/pm.h5
-rw-r--r--arch/arm/plat-s3c/pm.c3
-rw-r--r--arch/arm/plat-s3c24xx/sleep.S10
5 files changed, 12 insertions, 10 deletions
diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c
index 72f9686..87fc481 100644
--- a/arch/arm/mach-s3c2410/pm.c
+++ b/arch/arm/mach-s3c2410/pm.c
@@ -41,7 +41,7 @@ static void s3c2410_pm_prepare(void)
{
/* ensure at least GSTATUS3 has the resume address */
- __raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2410_GSTATUS3);
+ __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2410_GSTATUS3);
S3C_PMDBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3));
S3C_PMDBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4));
diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c
index 50d8054..72c266a 100644
--- a/arch/arm/mach-s3c2412/mach-jive.c
+++ b/arch/arm/mach-s3c2412/mach-jive.c
@@ -494,7 +494,7 @@ static int jive_pm_suspend(struct sys_device *sd, pm_message_t state)
* correct address to resume from. */
__raw_writel(0x2BED, S3C2412_INFORM0);
- __raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2412_INFORM1);
+ __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1);
return 0;
}
diff --git a/arch/arm/plat-s3c/include/plat/pm.h b/arch/arm/plat-s3c/include/plat/pm.h
index a6104c8..f121a5a 100644
--- a/arch/arm/plat-s3c/include/plat/pm.h
+++ b/arch/arm/plat-s3c/include/plat/pm.h
@@ -46,9 +46,10 @@ extern unsigned long s3c_pm_flags;
/* from sleep.S */
-extern int s3c2410_cpu_save(unsigned long *saveblk);
+extern int s3c_cpu_save(unsigned long *saveblk);
+extern void s3c_cpu_resume(void);
+
extern void s3c2410_cpu_suspend(void);
-extern void s3c2410_cpu_resume(void);
extern unsigned long s3c_sleep_save_phys;
diff --git a/arch/arm/plat-s3c/pm.c b/arch/arm/plat-s3c/pm.c
index e82ec62..e320b0f 100644
--- a/arch/arm/plat-s3c/pm.c
+++ b/arch/arm/plat-s3c/pm.c
@@ -280,8 +280,9 @@ static int s3c_pm_enter(suspend_state_t state)
* we resume as it saves its own register state, so use the return
* code to differentiate return from save and return from sleep */
- if (s3c2410_cpu_save(regs_save) == 0) {
+ if (s3c_cpu_save(regs_save) == 0) {
flush_cache_all();
+ S3C_PMDBG("preparing to sleep\n");
pm_cpu_sleep();
}
diff --git a/arch/arm/plat-s3c24xx/sleep.S b/arch/arm/plat-s3c24xx/sleep.S
index 7c1955f..ecb830b 100644
--- a/arch/arm/plat-s3c24xx/sleep.S
+++ b/arch/arm/plat-s3c24xx/sleep.S
@@ -41,7 +41,7 @@
.text
- /* s3c2410_cpu_save
+ /* s3c_cpu_save
*
* save enough of the CPU state to allow us to re-start
* pm.c code. as we store items like the sp/lr, we will
@@ -59,7 +59,7 @@
* 1 => resumed from sleep
*/
-ENTRY(s3c2410_cpu_save)
+ENTRY(s3c_cpu_save)
stmfd sp!, { r4 - r12, lr }
@@ store co-processor registers
@@ -99,12 +99,12 @@ s3c_sleep_save_phys:
/* sleep magic, to allow the bootloader to check for an valid
* image to resume to. Must be the first word before the
- * s3c2410_cpu_resume entry.
+ * s3c_cpu_resume entry.
*/
.word 0x2bedf00d
- /* s3c2410_cpu_resume
+ /* s3c_cpu_resume
*
* resume code entry for bootloader to call
*
@@ -113,7 +113,7 @@ s3c_sleep_save_phys:
* must not write to the code segment (code is read-only)
*/
-ENTRY(s3c2410_cpu_resume)
+ENTRY(s3c_cpu_resume)
mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
msr cpsr_c, r0
OpenPOWER on IntegriCloud