summaryrefslogtreecommitdiffstats
path: root/arch
diff options
context:
space:
mode:
authorPaul Mundt <lethal@linux-sh.org>2010-04-02 16:13:27 +0900
committerPaul Mundt <lethal@linux-sh.org>2010-04-02 16:13:27 +0900
commitbe97d758e5728099e95fe229866d5c6c900d3092 (patch)
tree5c5a3fa4b7978857562d730e3101181b5fbebb9f /arch
parent5dd6ef5050c5012267e2b84f3d82ba85cdb5ca32 (diff)
downloadop-kernel-dev-be97d758e5728099e95fe229866d5c6c900d3092.zip
op-kernel-dev-be97d758e5728099e95fe229866d5c6c900d3092.tar.gz
sh: Fix up the SH-3 build for recent TLB changes.
While the MMUCR.URB and ITLB/UTLB differentiation works fine for all SH-4 and later TLBs, these features are absent on SH-3. This splits out local_flush_tlb_all() in to SH-4 and PTEAEX copies while restoring the old SH-3 one, subsequently fixing up the build. This will probably want some further reordering and tidying in the future, but that's out of scope at present. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/sh/mm/tlb-pteaex.c28
-rw-r--r--arch/sh/mm/tlb-sh3.c19
-rw-r--r--arch/sh/mm/tlb-sh4.c28
-rw-r--r--arch/sh/mm/tlbflush_32.c28
4 files changed, 75 insertions, 28 deletions
diff --git a/arch/sh/mm/tlb-pteaex.c b/arch/sh/mm/tlb-pteaex.c
index bdd0982..b71db6a 100644
--- a/arch/sh/mm/tlb-pteaex.c
+++ b/arch/sh/mm/tlb-pteaex.c
@@ -77,3 +77,31 @@ void local_flush_tlb_one(unsigned long asid, unsigned long page)
__raw_writel(asid, MMU_ITLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT);
back_to_cached();
}
+
+void local_flush_tlb_all(void)
+{
+ unsigned long flags, status;
+ int i;
+
+ /*
+ * Flush all the TLB.
+ */
+ local_irq_save(flags);
+ jump_to_uncached();
+
+ status = __raw_readl(MMUCR);
+ status = ((status & MMUCR_URB) >> MMUCR_URB_SHIFT);
+
+ if (status == 0)
+ status = MMUCR_URB_NENTRIES;
+
+ for (i = 0; i < status; i++)
+ __raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8));
+
+ for (i = 0; i < 4; i++)
+ __raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8));
+
+ back_to_cached();
+ ctrl_barrier();
+ local_irq_restore(flags);
+}
diff --git a/arch/sh/mm/tlb-sh3.c b/arch/sh/mm/tlb-sh3.c
index 4f5f7cb..7a940db 100644
--- a/arch/sh/mm/tlb-sh3.c
+++ b/arch/sh/mm/tlb-sh3.c
@@ -77,3 +77,22 @@ void local_flush_tlb_one(unsigned long asid, unsigned long page)
for (i = 0; i < ways; i++)
__raw_writel(data, addr + (i << 8));
}
+
+void local_flush_tlb_all(void)
+{
+ unsigned long flags, status;
+
+ /*
+ * Flush all the TLB.
+ *
+ * Write to the MMU control register's bit:
+ * TF-bit for SH-3, TI-bit for SH-4.
+ * It's same position, bit #2.
+ */
+ local_irq_save(flags);
+ status = __raw_readl(MMUCR);
+ status |= 0x04;
+ __raw_writel(status, MMUCR);
+ ctrl_barrier();
+ local_irq_restore(flags);
+}
diff --git a/arch/sh/mm/tlb-sh4.c b/arch/sh/mm/tlb-sh4.c
index ccac77f..cfdf793 100644
--- a/arch/sh/mm/tlb-sh4.c
+++ b/arch/sh/mm/tlb-sh4.c
@@ -80,3 +80,31 @@ void local_flush_tlb_one(unsigned long asid, unsigned long page)
__raw_writel(data, addr);
back_to_cached();
}
+
+void local_flush_tlb_all(void)
+{
+ unsigned long flags, status;
+ int i;
+
+ /*
+ * Flush all the TLB.
+ */
+ local_irq_save(flags);
+ jump_to_uncached();
+
+ status = __raw_readl(MMUCR);
+ status = ((status & MMUCR_URB) >> MMUCR_URB_SHIFT);
+
+ if (status == 0)
+ status = MMUCR_URB_NENTRIES;
+
+ for (i = 0; i < status; i++)
+ __raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8));
+
+ for (i = 0; i < 4; i++)
+ __raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8));
+
+ back_to_cached();
+ ctrl_barrier();
+ local_irq_restore(flags);
+}
diff --git a/arch/sh/mm/tlbflush_32.c b/arch/sh/mm/tlbflush_32.c
index 77dc5ef..3fbe03c 100644
--- a/arch/sh/mm/tlbflush_32.c
+++ b/arch/sh/mm/tlbflush_32.c
@@ -119,31 +119,3 @@ void local_flush_tlb_mm(struct mm_struct *mm)
local_irq_restore(flags);
}
}
-
-void local_flush_tlb_all(void)
-{
- unsigned long flags, status;
- int i;
-
- /*
- * Flush all the TLB.
- */
- local_irq_save(flags);
- jump_to_uncached();
-
- status = __raw_readl(MMUCR);
- status = ((status & MMUCR_URB) >> MMUCR_URB_SHIFT);
-
- if (status == 0)
- status = MMUCR_URB_NENTRIES;
-
- for (i = 0; i < status; i++)
- __raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8));
-
- for (i = 0; i < 4; i++)
- __raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8));
-
- back_to_cached();
- ctrl_barrier();
- local_irq_restore(flags);
-}
OpenPOWER on IntegriCloud