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| author | Sekhar Nori <nsekhar@ti.com> | 2009-11-16 17:21:34 +0530 |
|---|---|---|
| committer | Kevin Hilman <khilman@deeprootsystems.com> | 2010-02-04 13:29:35 -0800 |
| commit | 7ec4b24326ec9b0467ab23b0417ec6b63e8e5524 (patch) | |
| tree | c724879a4842d625a7d1432e90d5f03dd192cf32 /arch | |
| parent | 9a219a9ecf49ab156df4c18267ade4d468d9930e (diff) | |
| download | op-kernel-dev-7ec4b24326ec9b0467ab23b0417ec6b63e8e5524.zip op-kernel-dev-7ec4b24326ec9b0467ab23b0417ec6b63e8e5524.tar.gz | |
davinci: move DDR2 controller defines to memory.h
Move defintions of DDR2 controller registers to memory.h
from cpuidle.c. The motivation behind the change is to be
able to use these defintions in assembly code that puts
DDR2 in self-refresh and enables the SoC to enter suspend
state.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-davinci/cpuidle.c | 5 | ||||
| -rw-r--r-- | arch/arm/mach-davinci/include/mach/memory.h | 4 |
2 files changed, 5 insertions, 4 deletions
diff --git a/arch/arm/mach-davinci/cpuidle.c b/arch/arm/mach-davinci/cpuidle.c index 97a90f3..beda3b5 100644 --- a/arch/arm/mach-davinci/cpuidle.c +++ b/arch/arm/mach-davinci/cpuidle.c @@ -19,6 +19,7 @@ #include <asm/proc-fns.h> #include <mach/cpuidle.h> +#include <mach/memory.h> #define DAVINCI_CPUIDLE_MAX_STATES 2 @@ -39,10 +40,6 @@ static struct cpuidle_driver davinci_idle_driver = { static DEFINE_PER_CPU(struct cpuidle_device, davinci_cpuidle_device); static void __iomem *ddr2_reg_base; -#define DDR2_SDRCR_OFFSET 0xc -#define DDR2_SRPD_BIT BIT(23) -#define DDR2_LPMODEN_BIT BIT(31) - static void davinci_save_ddr_power(int enter, bool pdown) { u32 val; diff --git a/arch/arm/mach-davinci/include/mach/memory.h b/arch/arm/mach-davinci/include/mach/memory.h index 80309ae..7aeaf46 100644 --- a/arch/arm/mach-davinci/include/mach/memory.h +++ b/arch/arm/mach-davinci/include/mach/memory.h @@ -31,6 +31,10 @@ #define PHYS_OFFSET DAVINCI_DDR_BASE #endif +#define DDR2_SDRCR_OFFSET 0xc +#define DDR2_SRPD_BIT BIT(23) +#define DDR2_LPMODEN_BIT BIT(31) + /* * Increase size of DMA-consistent memory region */ |
