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| author | LEROY Christophe <christophe.leroy@c-s.fr> | 2014-09-19 10:36:10 +0200 |
|---|---|---|
| committer | Scott Wood <scottwood@freescale.com> | 2014-11-07 18:10:45 -0600 |
| commit | c51a6821bdbc9068adda93b3b8ee65df8e4642a6 (patch) | |
| tree | 0ff47308ec2dbb867a316d3eaf57d2e965041922 /arch | |
| parent | 83c17ba35e0306e671b5c9ab622535f23a9a3e78 (diff) | |
| download | op-kernel-dev-c51a6821bdbc9068adda93b3b8ee65df8e4642a6.zip op-kernel-dev-c51a6821bdbc9068adda93b3b8ee65df8e4642a6.tar.gz | |
powerpc/8xx: Invalidate non present TLB as early as possible
8xx sometimes need to load a invalid/non-present TLBs in
it DTLB asm handler.
These must be invalidated separaly as linux mm doesn't.
Commit 5efab4a02c89c252fb4cce097aafde5f8208dbfe was invalidating them in
arch/powerpc/mm/fault.c.
This patch does the invalidation earlier in order to free the TLB as soon as
possible. This also has the advantage of removing some 8xx specific code from
fault.c
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/powerpc/kernel/head_8xx.S | 15 | ||||
| -rw-r--r-- | arch/powerpc/mm/fault.c | 7 |
2 files changed, 10 insertions, 12 deletions
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index acf6d7e..d99aac0 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -475,8 +475,11 @@ InstructionTLBError1: EXCEPTION_PROLOG_2 mr r4,r12 mr r5,r9 + andis. r10,r5,0x4000 + beq+ 1f + tlbie r4 /* 0x400 is InstructionAccess exception, needed by bad_page_fault() */ - EXC_XFER_LITE(0x400, handle_page_fault) +1: EXC_XFER_LITE(0x400, handle_page_fault) /* This is the data TLB error on the MPC8xx. This could be due to * many reasons, including a dirty update to a pte. We bail out to @@ -492,11 +495,13 @@ DataTLBError: DARFixed:/* Return from dcbx instruction bug workaround */ EXCEPTION_PROLOG_1 EXCEPTION_PROLOG_2 - mfspr r10,SPRN_DSISR - stw r10,_DSISR(r11) - mr r5,r10 + mfspr r5,SPRN_DSISR + stw r5,_DSISR(r11) mfspr r4,SPRN_DAR - li r10,RPN_PATTERN + andis. r10,r5,0x4000 + beq+ 1f + tlbie r4 +1: li r10,RPN_PATTERN mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */ /* 0x300 is DataAccess exception, needed by bad_page_fault() */ EXC_XFER_LITE(0x300, handle_page_fault) diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c index 08d659a..eb79907 100644 --- a/arch/powerpc/mm/fault.c +++ b/arch/powerpc/mm/fault.c @@ -43,7 +43,6 @@ #include <asm/tlbflush.h> #include <asm/siginfo.h> #include <asm/debug.h> -#include <mm/mmu_decl.h> #include "icswx.h" @@ -380,12 +379,6 @@ good_area: goto bad_area; #endif /* CONFIG_6xx */ #if defined(CONFIG_8xx) - /* 8xx sometimes need to load a invalid/non-present TLBs. - * These must be invalidated separately as linux mm don't. - */ - if (error_code & 0x40000000) /* no translation? */ - _tlbil_va(address, 0, 0, 0); - /* The MPC8xx seems to always set 0x80000000, which is * "undefined". Of those that can be set, this is the only * one which seems bad. |
