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authorThomas Bogendoerfer <tsbogend@alpha.franken.de>2007-11-27 19:31:33 +0100
committerRalf Baechle <ralf@linux-mips.org>2008-01-29 10:14:58 +0000
commitc7c6b39050aed4af913c17970ebfb592bae757fc (patch)
treefaaad45cd4b3ef2f582c6b47a5082e9eee2853fd /arch
parent930bff882296c02ca81db108672ef4ca06c37db5 (diff)
downloadop-kernel-dev-c7c6b39050aed4af913c17970ebfb592bae757fc.zip
op-kernel-dev-c7c6b39050aed4af913c17970ebfb592bae757fc.tar.gz
[MIPS] Use correct dma flushing in dma_cache_sync()
Not cache coherent R10k systems (like IP28) need to do real cache invalidates in dma_cache_sync(). Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/mm/dma-default.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index 810535d..ae39dd8 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -383,7 +383,7 @@ void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
BUG_ON(direction == DMA_NONE);
if (!plat_device_is_coherent(dev))
- dma_cache_wback_inv((unsigned long)vaddr, size);
+ __dma_sync((unsigned long)vaddr, size, direction);
}
EXPORT_SYMBOL(dma_cache_sync);
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