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authorDmitri Vorobiev <dmitri.vorobiev@movial.fi>2008-06-18 10:18:21 +0300
committerRalf Baechle <ralf@linux-mips.org>2008-07-15 18:44:31 +0100
commit7afed6a6c92fadedde8474bbfd92d6debc5e23b0 (patch)
treeea745722c02f93ddabc678be08805845cb705524 /arch
parentd58eaab5a01b9cf1819ec57271ac214a39bf6278 (diff)
downloadop-kernel-dev-7afed6a6c92fadedde8474bbfd92d6debc5e23b0.zip
op-kernel-dev-7afed6a6c92fadedde8474bbfd92d6debc5e23b0.tar.gz
[MIPS] A few cleanups in malta_int.c
Both the fill_ipi_map() routine and the gic_intr_map array defined in arch/mips/mips-boards/malta/malta_int.c are not used outside of the latter file. Thus, these objects can become static. Moreover, these two objects are used by the MT code only, which is why this patch adds the appropriate ifdef. While at it, this patch removes an unnecessary preprocessing macro in favor of the commonly used ARRAY_SIZE. Successfully tested using a Qemu-emulated Malta board for both SMP and UP kernels. Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@movial.fi> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/mips-boards/malta/malta_int.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c
index 4b5694e..b393982 100644
--- a/arch/mips/mips-boards/malta/malta_int.c
+++ b/arch/mips/mips-boards/malta/malta_int.c
@@ -363,6 +363,7 @@ static msc_irqmap_t __initdata msc_eicirqmap[] = {
static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap);
+#if defined(CONFIG_MIPS_MT_SMP)
/*
* This GIC specific tabular array defines the association between External
* Interrupts and CPUs/Core Interrupts. The nature of the External
@@ -394,6 +395,7 @@ static struct gic_intr_map gic_intr_map[] = {
{ GIC_EXT_INTR(22), 3, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, 1 },
{ GIC_EXT_INTR(23), 3, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, 1 },
};
+#endif
/*
* GCMP needs to be detected before any SMP initialisation
@@ -412,7 +414,8 @@ int __init gcmp_probe(unsigned long addr, unsigned long size)
return gcmp_present;
}
-void __init fill_ipi_map(void)
+#if defined(CONFIG_MIPS_MT_SMP)
+static void __init fill_ipi_map(void)
{
int i;
@@ -422,6 +425,7 @@ void __init fill_ipi_map(void)
(1 << (gic_intr_map[i].pin + 2));
}
}
+#endif
void __init arch_init_irq(void)
{
@@ -527,7 +531,6 @@ void __init arch_init_irq(void)
.call = GIC_IPI_EXT_INTR_CALLFNC_VPE3
}
};
-#define NIPI ARRAY_SIZE(ipiirq)
fill_ipi_map();
gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
if (!gcmp_present) {
@@ -549,7 +552,7 @@ void __init arch_init_irq(void)
printk("CPU%d: status register now %08x\n", smp_processor_id(), read_c0_status());
write_c0_status(0x1100dc00);
printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status());
- for (i = 0; i < NIPI; i++) {
+ for (i = 0; i < ARRAY_SIZE(ipiirq); i++) {
setup_irq(MIPS_GIC_IRQ_BASE + ipiirq[i].resched, &irq_resched);
setup_irq(MIPS_GIC_IRQ_BASE + ipiirq[i].call, &irq_call);
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