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| author | Gabor Juhos <juhosg@openwrt.org> | 2013-01-29 08:19:12 +0000 |
|---|---|---|
| committer | John Crispin <blogic@openwrt.org> | 2013-02-17 01:25:27 +0100 |
| commit | 8838becdf5f7261d7f5dfbbe957fe9b9ed188aec (patch) | |
| tree | 9a2bfbe783c71cba97fff61978f96a815876cc98 /arch | |
| parent | 778eeb1b199b85bec79b49ac483b013e270636ea (diff) | |
| download | op-kernel-dev-8838becdf5f7261d7f5dfbbe957fe9b9ed188aec.zip op-kernel-dev-8838becdf5f7261d7f5dfbbe957fe9b9ed188aec.tar.gz | |
MIPS: ath79: fix GPIO function selection for AR934x SoCs
GPIO function selection is not working on the AR934x
SoCs because the offset of the function selection
register is different on those.
Add a helper routine which returns the correct
register address based on the SoC type, and use
that in the 'ath79_gpio_function_*' routines.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4870/
Signed-off-by: John Crispin <blogic@openwrt.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/mips/ath79/gpio.c | 38 | ||||
| -rw-r--r-- | arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 2 |
2 files changed, 28 insertions, 12 deletions
diff --git a/arch/mips/ath79/gpio.c b/arch/mips/ath79/gpio.c index 48fe762..662a10e 100644 --- a/arch/mips/ath79/gpio.c +++ b/arch/mips/ath79/gpio.c @@ -137,47 +137,61 @@ static struct gpio_chip ath79_gpio_chip = { .base = 0, }; +static void __iomem *ath79_gpio_get_function_reg(void) +{ + u32 reg = 0; + + if (soc_is_ar71xx() || + soc_is_ar724x() || + soc_is_ar913x() || + soc_is_ar933x()) + reg = AR71XX_GPIO_REG_FUNC; + else if (soc_is_ar934x()) + reg = AR934X_GPIO_REG_FUNC; + else + BUG(); + + return ath79_gpio_base + reg; +} + void ath79_gpio_function_enable(u32 mask) { - void __iomem *base = ath79_gpio_base; + void __iomem *reg = ath79_gpio_get_function_reg(); unsigned long flags; spin_lock_irqsave(&ath79_gpio_lock, flags); - __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) | mask, - base + AR71XX_GPIO_REG_FUNC); + __raw_writel(__raw_readl(reg) | mask, reg); /* flush write */ - __raw_readl(base + AR71XX_GPIO_REG_FUNC); + __raw_readl(reg); spin_unlock_irqrestore(&ath79_gpio_lock, flags); } void ath79_gpio_function_disable(u32 mask) { - void __iomem *base = ath79_gpio_base; + void __iomem *reg = ath79_gpio_get_function_reg(); unsigned long flags; spin_lock_irqsave(&ath79_gpio_lock, flags); - __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~mask, - base + AR71XX_GPIO_REG_FUNC); + __raw_writel(__raw_readl(reg) & ~mask, reg); /* flush write */ - __raw_readl(base + AR71XX_GPIO_REG_FUNC); + __raw_readl(reg); spin_unlock_irqrestore(&ath79_gpio_lock, flags); } void ath79_gpio_function_setup(u32 set, u32 clear) { - void __iomem *base = ath79_gpio_base; + void __iomem *reg = ath79_gpio_get_function_reg(); unsigned long flags; spin_lock_irqsave(&ath79_gpio_lock, flags); - __raw_writel((__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~clear) | set, - base + AR71XX_GPIO_REG_FUNC); + __raw_writel((__raw_readl(reg) & ~clear) | set, reg); /* flush write */ - __raw_readl(base + AR71XX_GPIO_REG_FUNC); + __raw_readl(reg); spin_unlock_irqrestore(&ath79_gpio_lock, flags); } diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index a5e0f17..7d44b5d 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -401,6 +401,8 @@ #define AR71XX_GPIO_REG_INT_ENABLE 0x24 #define AR71XX_GPIO_REG_FUNC 0x28 +#define AR934X_GPIO_REG_FUNC 0x6c + #define AR71XX_GPIO_COUNT 16 #define AR7240_GPIO_COUNT 18 #define AR7241_GPIO_COUNT 20 |
