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authorLinus Walleij <linus.walleij@linaro.org>2012-12-26 01:38:28 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2013-01-02 10:35:06 +0000
commitf5565295892eb93c3191aa241405fe8b685542d6 (patch)
treec1d6d0269df2ec2e23e290768530073f4121e355 /arch
parent62e4d357aae0c7438c537bdb1c86909d7cac2663 (diff)
downloadop-kernel-dev-f5565295892eb93c3191aa241405fe8b685542d6.zip
op-kernel-dev-f5565295892eb93c3191aa241405fe8b685542d6.tar.gz
ARM: 7610/1: versatile: bump IRQ numbers
The Versatile starts to register Linux IRQ numbers from offset 0 which is illegal, since this is NO_IRQ. Bump all hard-coded IRQs by 32 to get rid of the problem. Cc: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-versatile/include/mach/irqs.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/mach-versatile/include/mach/irqs.h b/arch/arm/mach-versatile/include/mach/irqs.h
index bf44c61..0fd771c 100644
--- a/arch/arm/mach-versatile/include/mach/irqs.h
+++ b/arch/arm/mach-versatile/include/mach/irqs.h
@@ -25,7 +25,7 @@
* IRQ interrupts definitions are the same as the INT definitions
* held within platform.h
*/
-#define IRQ_VIC_START 0
+#define IRQ_VIC_START 32
#define IRQ_WDOGINT (IRQ_VIC_START + INT_WDOGINT)
#define IRQ_SOFTINT (IRQ_VIC_START + INT_SOFTINT)
#define IRQ_COMMRx (IRQ_VIC_START + INT_COMMRx)
@@ -100,7 +100,7 @@
/*
* Secondary interrupt controller
*/
-#define IRQ_SIC_START 32
+#define IRQ_SIC_START 64
#define IRQ_SIC_MMCI0B (IRQ_SIC_START + SIC_INT_MMCI0B)
#define IRQ_SIC_MMCI1B (IRQ_SIC_START + SIC_INT_MMCI1B)
#define IRQ_SIC_KMI0 (IRQ_SIC_START + SIC_INT_KMI0)
@@ -120,7 +120,7 @@
#define IRQ_SIC_PCI1 (IRQ_SIC_START + SIC_INT_PCI1)
#define IRQ_SIC_PCI2 (IRQ_SIC_START + SIC_INT_PCI2)
#define IRQ_SIC_PCI3 (IRQ_SIC_START + SIC_INT_PCI3)
-#define IRQ_SIC_END 63
+#define IRQ_SIC_END 95
#define IRQ_GPIO0_START (IRQ_SIC_END + 1)
#define IRQ_GPIO0_END (IRQ_GPIO0_START + 31)
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