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| author | Arnd Bergmann <arnd.bergmann@de.ibm.com> | 2006-06-23 20:57:50 +0200 |
|---|---|---|
| committer | Paul Mackerras <paulus@samba.org> | 2006-06-28 15:18:37 +1000 |
| commit | 2cd90bc8fba8720ef7f3fdfd1e0c1a5397a18271 (patch) | |
| tree | b779ce75a774e3286c39188978e86c0bb047168b /arch | |
| parent | 4da30d15b6d5036b0d96422d6946ca758111fae3 (diff) | |
| download | op-kernel-dev-2cd90bc8fba8720ef7f3fdfd1e0c1a5397a18271.zip op-kernel-dev-2cd90bc8fba8720ef7f3fdfd1e0c1a5397a18271.tar.gz | |
[POWERPC] spufs: fix class0 interrupt assignment
The class zero interrupt handling for spus was confusing alignment and
error interrupts, so swap them.
Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/powerpc/platforms/cell/spu_base.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/powerpc/platforms/cell/spu_base.c b/arch/powerpc/platforms/cell/spu_base.c index db82f50..b306723 100644 --- a/arch/powerpc/platforms/cell/spu_base.c +++ b/arch/powerpc/platforms/cell/spu_base.c @@ -168,12 +168,12 @@ spu_irq_class_0_bottom(struct spu *spu) stat &= mask; - if (stat & 1) /* invalid MFC DMA */ - __spu_trap_invalid_dma(spu); - - if (stat & 2) /* invalid DMA alignment */ + if (stat & 1) /* invalid DMA alignment */ __spu_trap_dma_align(spu); + if (stat & 2) /* invalid MFC DMA */ + __spu_trap_invalid_dma(spu); + if (stat & 4) /* error on SPU */ __spu_trap_error(spu); |
