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authorCatalin Marinas <catalin.marinas@arm.com>2007-02-05 14:48:08 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-02-08 14:49:40 +0000
commit953233dc9958ba2b29753d0f24e37a33a076a5f6 (patch)
treeb9cc9ddc82722dc79a72a8c6f4977566ec2e0384 /arch
parent7f8e33546d17c7d8849be3a6623c3b6b3c9b588b (diff)
downloadop-kernel-dev-953233dc9958ba2b29753d0f24e37a33a076a5f6.zip
op-kernel-dev-953233dc9958ba2b29753d0f24e37a33a076a5f6.tar.gz
[ARM] 4134/1: Add generic support for outer caches
The outer cache can be L2 as on RealView/EB MPCore platform or even L3 or further on ARMv7 cores. This patch adds the generic support for flushing the outer cache in the DMA operations. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/common/dmabounce.c1
-rw-r--r--arch/arm/kernel/setup.c3
-rw-r--r--arch/arm/mm/Kconfig3
-rw-r--r--arch/arm/mm/consistent.c6
4 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c
index 272702a..b4748e3 100644
--- a/arch/arm/common/dmabounce.c
+++ b/arch/arm/common/dmabounce.c
@@ -338,6 +338,7 @@ unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
*/
ptr = (unsigned long)buf->ptr;
dmac_clean_range(ptr, ptr + size);
+ outer_clean_range(__pa(ptr), __pa(ptr) + size);
}
free_safe_buffer(device_info, buf);
}
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index bbab134..243aea4 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -88,6 +88,9 @@ struct cpu_user_fns cpu_user;
#ifdef MULTI_CACHE
struct cpu_cache_fns cpu_cache;
#endif
+#ifdef CONFIG_OUTER_CACHE
+struct outer_cache_fns outer_cache;
+#endif
struct stack {
u32 irq[3];
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index aade2f7..a84eed9 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -609,3 +609,6 @@ config NEEDS_SYSCALL_FOR_CMPXCHG
Forget about fast user space cmpxchg support.
It is just not possible.
+config OUTER_CACHE
+ bool
+ default n
diff --git a/arch/arm/mm/consistent.c b/arch/arm/mm/consistent.c
index 6a9c362..83bd035 100644
--- a/arch/arm/mm/consistent.c
+++ b/arch/arm/mm/consistent.c
@@ -208,6 +208,7 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
unsigned long kaddr = (unsigned long)page_address(page);
memset(page_address(page), 0, size);
dmac_flush_range(kaddr, kaddr + size);
+ outer_flush_range(__pa(kaddr), __pa(kaddr) + size);
}
/*
@@ -485,15 +486,20 @@ void consistent_sync(void *vaddr, size_t size, int direction)
unsigned long start = (unsigned long)vaddr;
unsigned long end = start + size;
+ BUG_ON(!virt_addr_valid(start) || !virt_addr_valid(end));
+
switch (direction) {
case DMA_FROM_DEVICE: /* invalidate only */
dmac_inv_range(start, end);
+ outer_inv_range(__pa(start), __pa(end));
break;
case DMA_TO_DEVICE: /* writeback only */
dmac_clean_range(start, end);
+ outer_clean_range(__pa(start), __pa(end));
break;
case DMA_BIDIRECTIONAL: /* writeback and invalidate */
dmac_flush_range(start, end);
+ outer_flush_range(__pa(start), __pa(end));
break;
default:
BUG();
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