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authorMadhu <madhu.cr@ti.com>2009-11-22 10:11:07 -0800
committerTony Lindgren <tony@atomide.com>2009-11-22 10:24:32 -0800
commit41fd03d66e6ae4430a0fdf7c62692a7b20b6ee6b (patch)
tree8dfa1a7c78a9be40eccede335f2dddabac1029ee /arch
parent4596d14ad88bbacc80970cb964b8f3d6ade7e305 (diff)
downloadop-kernel-dev-41fd03d66e6ae4430a0fdf7c62692a7b20b6ee6b.zip
op-kernel-dev-41fd03d66e6ae4430a0fdf7c62692a7b20b6ee6b.tar.gz
omap3630: Configure HSMMC1 to 4-bit
The HSMMC1 controller on omap3630 supprts only 4-bit mode. If cpu is 3630 configure HSMMC1 wires to 4-bit. Signed-off-by: Madhusudhan Chikkature <madhu.cr@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-omap2/mmc-twl4030.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/mmc-twl4030.c b/arch/arm/mach-omap2/mmc-twl4030.c
index 3403914..7bef170 100644
--- a/arch/arm/mach-omap2/mmc-twl4030.c
+++ b/arch/arm/mach-omap2/mmc-twl4030.c
@@ -489,6 +489,12 @@ void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers)
/* on-chip level shifting via PBIAS0/PBIAS1 */
mmc->slots[0].set_power = twl_mmc1_set_power;
mmc->slots[0].set_sleep = twl_mmc1_set_sleep;
+
+ /* Omap3630 HSMMC1 supports only 4-bit */
+ if (cpu_is_omap3630() && c->wires > 4) {
+ c->wires = 4;
+ mmc->slots[0].wires = c->wires;
+ }
break;
case 2:
if (c->ext_clock)
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