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| author | David Daney <ddaney@caviumnetworks.com> | 2008-12-11 15:33:24 -0800 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2009-01-11 09:57:21 +0000 |
| commit | ed918c2daf9ef4c3b52f75736c3a652e5160c8ad (patch) | |
| tree | 7297a323dae5e9564b7f45a74f17d599a58c50b7 /arch | |
| parent | f9bb4cf37ad3f7dec63abc5db688dd1e9df0056c (diff) | |
| download | op-kernel-dev-ed918c2daf9ef4c3b52f75736c3a652e5160c8ad.zip op-kernel-dev-ed918c2daf9ef4c3b52f75736c3a652e5160c8ad.tar.gz | |
MIPS: Add Cavium OCTEON specific register definitions to mipsregs.h
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/mips/include/asm/mipsregs.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 9316324..207d098 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -1000,6 +1000,26 @@ do { \ #define read_c0_ebase() __read_32bit_c0_register($15, 1) #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) + +/* Cavium OCTEON (cnMIPS) */ +#define read_c0_cvmcount() __read_ulong_c0_register($9, 6) +#define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val) + +#define read_c0_cvmctl() __read_64bit_c0_register($9, 7) +#define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val) + +#define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7) +#define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val) +/* + * The cacheerr registers are not standardized. On OCTEON, they are + * 64 bits wide. + */ +#define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0) +#define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val) + +#define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1) +#define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) + /* * Macros to access the floating point coprocessor control registers */ |
