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authorBrian Gerst <brgerst@gmail.com>2009-01-27 12:56:48 +0900
committerTejun Heo <tj@kernel.org>2009-01-27 12:56:48 +0900
commit1825b8edc2034c012ae48f797d74efd1bd9d4f72 (patch)
treede6d7d8c53df7dd476583a9158e753a3237ee61b /arch
parentb2d2f4312b117a6cc647c8521e2643a88771f757 (diff)
downloadop-kernel-dev-1825b8edc2034c012ae48f797d74efd1bd9d4f72.zip
op-kernel-dev-1825b8edc2034c012ae48f797d74efd1bd9d4f72.tar.gz
x86: remove extra barriers from load_gs_base()
Impact: optimization mb() generates an mfence instruction, which is not needed here. Only a compiler barrier is needed, and that is handled by the memory clobber in the wrmsrl function. Signed-off-by: Brian Gerst <brgerst@gmail.com> Signed-off-by: Tejun Heo <tj@kernel.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/x86/include/asm/processor.h3
1 files changed, 0 insertions, 3 deletions
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 32c30b0..794234e 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -397,10 +397,7 @@ DECLARE_PER_CPU(char *, irq_stack_ptr);
static inline void load_gs_base(int cpu)
{
- /* Memory clobbers used to order pda/percpu accesses */
- mb();
wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
- mb();
}
#endif
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