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| author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2006-06-21 13:51:41 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-06-22 10:24:24 +0100 |
| commit | 1a6be26d5b1a86f66ef60e5b73bae64d50873724 (patch) | |
| tree | c56cc8ed28d9d9dc062043a0a7862e1692908770 /arch | |
| parent | d6551e884cf66de072b81f8b6d23259462c40baf (diff) | |
| download | op-kernel-dev-1a6be26d5b1a86f66ef60e5b73bae64d50873724.zip op-kernel-dev-1a6be26d5b1a86f66ef60e5b73bae64d50873724.tar.gz | |
[ARM] Enable VFP to be built when non-VFP capable CPUs are selected
Since we pass flags to the compiler to control code generation based
on the least capable selected CPU, if we want to include VFP support,
we must tweak the assembler flags to allow the VFP instructions.
Moreover, we must not use the mrrc/mcrr versions since these will not
be recognised by the assembler.
We do not convert all instructions to the VFP-equivalent (yet) since
binutils appears to barf on "fmrx rn, fpinst" and doesn't provide any
other way (other than using the mrc equivalent) to encode this
instruction - which is rather a problem when you have a VFP
implementation which requires these instructions.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/vfp/Makefile | 5 | ||||
| -rw-r--r-- | arch/arm/vfp/vfphw.S | 4 |
2 files changed, 6 insertions, 3 deletions
diff --git a/arch/arm/vfp/Makefile b/arch/arm/vfp/Makefile index afabac3..7e136e7 100644 --- a/arch/arm/vfp/Makefile +++ b/arch/arm/vfp/Makefile @@ -7,6 +7,9 @@ # EXTRA_CFLAGS := -DDEBUG # EXTRA_AFLAGS := -DDEBUG +AFLAGS :=$(AFLAGS:-msoft-float=-Wa,-mfpu=softvfp+vfp) +LDFLAGS +=--no-warn-mismatch + obj-y += vfp.o -vfp-$(CONFIG_VFP) += entry.o vfpmodule.o vfphw.o vfpsingle.o vfpdouble.o +vfp-$(CONFIG_VFP) += vfpmodule.o entry.o vfphw.o vfpsingle.o vfpdouble.o diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S index a3f65b4..eb683cd 100644 --- a/arch/arm/vfp/vfphw.S +++ b/arch/arm/vfp/vfphw.S @@ -192,7 +192,7 @@ vfp_get_double: add pc, pc, r0, lsl #3 mov r0, r0 .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 - mrrc p11, 1, r0, r1, c\dr @ fmrrd r0, r1, d\dr + fmrrd r0, r1, d\dr mov pc, lr .endr @@ -206,6 +206,6 @@ vfp_put_double: add pc, pc, r0, lsl #3 mov r0, r0 .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 - mcrr p11, 1, r1, r2, c\dr @ fmdrr r1, r2, d\dr + fmdrr d\dr, r1, r2 mov pc, lr .endr |
