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authorKees Cook <kees.cook@canonical.com>2011-05-24 16:29:26 -0700
committerH. Peter Anvin <hpa@linux.intel.com>2011-05-24 16:37:27 -0700
commit7ccafc5f75c87853f3c49845d5a884f2376e03ce (patch)
tree21eb295d44de8edfae4c88860e4b51aa1169f696 /arch
parent37d8cb5478651b27779b9a80d024c614c452eae3 (diff)
downloadop-kernel-dev-7ccafc5f75c87853f3c49845d5a884f2376e03ce.zip
op-kernel-dev-7ccafc5f75c87853f3c49845d5a884f2376e03ce.tar.gz
x86, cpufeature: Update CPU feature RDRND to RDRAND
The Intel manual changed the name of the CPUID bit to match the instruction name. We should follow suit for sanity's sake. (See Intel SDM Volume 2, Table 3-20 "Feature Information Returned in the ECX Register".) [ hpa: we can only do this at this time because there are currently no CPUs with this feature on the market, hence this is pre-hardware enabling. However, Cc:'ing stable so that stable can present a consistent ABI. ] Signed-off-by: Kees Cook <kees.cook@canonical.com> Link: http://lkml.kernel.org/r/20110524232926.GA27728@outflux.net Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: <stable@kernel.org> v2.6.36-39
Diffstat (limited to 'arch')
-rw-r--r--arch/x86/include/asm/cpufeature.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 5dc6acc..71cc380 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -125,7 +125,7 @@
#define X86_FEATURE_OSXSAVE (4*32+27) /* "" XSAVE enabled in the OS */
#define X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */
#define X86_FEATURE_F16C (4*32+29) /* 16-bit fp conversions */
-#define X86_FEATURE_RDRND (4*32+30) /* The RDRAND instruction */
+#define X86_FEATURE_RDRAND (4*32+30) /* The RDRAND instruction */
#define X86_FEATURE_HYPERVISOR (4*32+31) /* Running on a hypervisor */
/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
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