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authorMarkos Chandras <markos.chandras@imgtec.com>2015-01-15 10:11:17 +0000
committerMarkos Chandras <markos.chandras@imgtec.com>2015-02-17 15:37:37 +0000
commite0d32f33e651a393a23826c06a9301917372f3e2 (patch)
treeb42ff5fbeeac5f838d6eb18d26efb6b39520cf8d /arch
parent7c151d3d5d7a032e08dbe86ad6088622391bf13e (diff)
downloadop-kernel-dev-e0d32f33e651a393a23826c06a9301917372f3e2.zip
op-kernel-dev-e0d32f33e651a393a23826c06a9301917372f3e2.tar.gz
MIPS: Handle MIPS IV, V and R2 FPU instructions on MIPS R6 as well
MIPS R2 FPU instructions are also present in MIPS R6 so amend the preprocessor definitions to take MIPS R6 into consideration. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/include/asm/cpu-features.h3
-rw-r--r--arch/mips/math-emu/cp1emu.c8
2 files changed, 6 insertions, 5 deletions
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index e686131..0d8208d 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -220,7 +220,8 @@
#define cpu_has_mips_4_5_r (cpu_has_mips_4 | cpu_has_mips_5_r)
#define cpu_has_mips_5_r (cpu_has_mips_5 | cpu_has_mips_r)
-#define cpu_has_mips_4_5_r2 (cpu_has_mips_4_5 | cpu_has_mips_r2)
+#define cpu_has_mips_4_5_r2_r6 (cpu_has_mips_4_5 | cpu_has_mips_r2 | \
+ cpu_has_mips_r6)
#define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2 | cpu_has_mips32r6)
#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2 | cpu_has_mips64r6)
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 3c341b08..b30bf65 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -1561,14 +1561,14 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
* achieve full IEEE-754 accuracy - however this emulator does.
*/
case frsqrt_op:
- if (!cpu_has_mips_4_5_r2)
+ if (!cpu_has_mips_4_5_r2_r6)
return SIGILL;
handler.u = fpemu_sp_rsqrt;
goto scopuop;
case frecip_op:
- if (!cpu_has_mips_4_5_r2)
+ if (!cpu_has_mips_4_5_r2_r6)
return SIGILL;
handler.u = fpemu_sp_recip;
@@ -1763,13 +1763,13 @@ copcsr:
* achieve full IEEE-754 accuracy - however this emulator does.
*/
case frsqrt_op:
- if (!cpu_has_mips_4_5_r2)
+ if (!cpu_has_mips_4_5_r2_r6)
return SIGILL;
handler.u = fpemu_dp_rsqrt;
goto dcopuop;
case frecip_op:
- if (!cpu_has_mips_4_5_r2)
+ if (!cpu_has_mips_4_5_r2_r6)
return SIGILL;
handler.u = fpemu_dp_recip;
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