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authorJaedon Shin <jaedon.shin@gmail.com>2016-08-19 11:52:29 +0900
committerRalf Baechle <ralf@linux-mips.org>2016-10-06 17:31:02 +0200
commitcfc8be04c36a1a6546b6f9cb8f02fd9f215c9d38 (patch)
tree8aa0bbf46d7c3485b992f4a7986659de6bf68882 /arch
parentb2420e2762e36ec3aab0c0b6b9ee277f7b1b48e2 (diff)
downloadop-kernel-dev-cfc8be04c36a1a6546b6f9cb8f02fd9f215c9d38.zip
op-kernel-dev-cfc8be04c36a1a6546b6f9cb8f02fd9f215c9d38.tar.gz
MIPS: BMIPS: Add support NAND device nodes
Adds NAND device nodes to BCM7xxx MIPS based SoCs. Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Jonas Gorski <jonas.gorski@gmail.com> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: MIPS Mailing List <linux-mips@linux-mips.org> Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14003/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/boot/dts/brcm/bcm7346.dtsi20
-rw-r--r--arch/mips/boot/dts/brcm/bcm7358.dtsi20
-rw-r--r--arch/mips/boot/dts/brcm/bcm7360.dtsi20
-rw-r--r--arch/mips/boot/dts/brcm/bcm7362.dtsi20
-rw-r--r--arch/mips/boot/dts/brcm/bcm7425.dtsi20
-rw-r--r--arch/mips/boot/dts/brcm/bcm7435.dtsi20
-rw-r--r--arch/mips/boot/dts/brcm/bcm97346dbsmb.dts5
-rw-r--r--arch/mips/boot/dts/brcm/bcm97358svmb.dts5
-rw-r--r--arch/mips/boot/dts/brcm/bcm97362svmb.dts5
-rw-r--r--arch/mips/boot/dts/brcm/bcm97425svmb.dts5
-rw-r--r--arch/mips/boot/dts/brcm/bcm97435svmb.dts5
-rw-r--r--arch/mips/boot/dts/brcm/bcm97xxx-nand-cs1-bch24.dtsi25
-rw-r--r--arch/mips/boot/dts/brcm/bcm97xxx-nand-cs1-bch4.dtsi25
13 files changed, 195 insertions, 0 deletions
diff --git a/arch/mips/boot/dts/brcm/bcm7346.dtsi b/arch/mips/boot/dts/brcm/bcm7346.dtsi
index 0da4f8a..72d9cff 100644
--- a/arch/mips/boot/dts/brcm/bcm7346.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7346.dtsi
@@ -372,6 +372,26 @@
status = "disabled";
};
+ hif_l2_intc: interrupt-controller@411000 {
+ compatible = "brcm,l2-intc";
+ reg = <0x411000 0x30>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&periph_intc>;
+ interrupts = <30>;
+ };
+
+ nand: nand@412800 {
+ compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg-names = "nand";
+ reg = <0x412800 0x400>;
+ interrupt-parent = <&hif_l2_intc>;
+ interrupts = <24>;
+ status = "disabled";
+ };
+
sata: sata@181000 {
compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
reg-names = "ahci", "top-ctrl";
diff --git a/arch/mips/boot/dts/brcm/bcm7358.dtsi b/arch/mips/boot/dts/brcm/bcm7358.dtsi
index aec1b2e..7f78bfa 100644
--- a/arch/mips/boot/dts/brcm/bcm7358.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7358.dtsi
@@ -298,5 +298,25 @@
interrupts = <66>;
status = "disabled";
};
+
+ hif_l2_intc: interrupt-controller@411000 {
+ compatible = "brcm,l2-intc";
+ reg = <0x411000 0x30>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&periph_intc>;
+ interrupts = <30>;
+ };
+
+ nand: nand@412800 {
+ compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg-names = "nand";
+ reg = <0x412800 0x400>;
+ interrupt-parent = <&hif_l2_intc>;
+ interrupts = <24>;
+ status = "disabled";
+ };
};
};
diff --git a/arch/mips/boot/dts/brcm/bcm7360.dtsi b/arch/mips/boot/dts/brcm/bcm7360.dtsi
index 9f72d34..64b9fd9 100644
--- a/arch/mips/boot/dts/brcm/bcm7360.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7360.dtsi
@@ -291,6 +291,26 @@
status = "disabled";
};
+ hif_l2_intc: interrupt-controller@411000 {
+ compatible = "brcm,l2-intc";
+ reg = <0x411000 0x30>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&periph_intc>;
+ interrupts = <30>;
+ };
+
+ nand: nand@412800 {
+ compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg-names = "nand";
+ reg = <0x412800 0x400>;
+ interrupt-parent = <&hif_l2_intc>;
+ interrupts = <24>;
+ status = "disabled";
+ };
+
sata: sata@181000 {
compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
reg-names = "ahci", "top-ctrl";
diff --git a/arch/mips/boot/dts/brcm/bcm7362.dtsi b/arch/mips/boot/dts/brcm/bcm7362.dtsi
index ff734f4..784d587 100644
--- a/arch/mips/boot/dts/brcm/bcm7362.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7362.dtsi
@@ -287,6 +287,26 @@
status = "disabled";
};
+ hif_l2_intc: interrupt-controller@411000 {
+ compatible = "brcm,l2-intc";
+ reg = <0x411000 0x30>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&periph_intc>;
+ interrupts = <30>;
+ };
+
+ nand: nand@412800 {
+ compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg-names = "nand";
+ reg = <0x412800 0x400>;
+ interrupt-parent = <&hif_l2_intc>;
+ interrupts = <24>;
+ status = "disabled";
+ };
+
sata: sata@181000 {
compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
reg-names = "ahci", "top-ctrl";
diff --git a/arch/mips/boot/dts/brcm/bcm7425.dtsi b/arch/mips/boot/dts/brcm/bcm7425.dtsi
index 1c8d3b4..7124c98 100644
--- a/arch/mips/boot/dts/brcm/bcm7425.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7425.dtsi
@@ -371,6 +371,26 @@
status = "disabled";
};
+ hif_l2_intc: interrupt-controller@41a000 {
+ compatible = "brcm,l2-intc";
+ reg = <0x41a000 0x30>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&periph_intc>;
+ interrupts = <24>;
+ };
+
+ nand: nand@41b800 {
+ compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg-names = "nand";
+ reg = <0x41b800 0x400>;
+ interrupt-parent = <&hif_l2_intc>;
+ interrupts = <24>;
+ status = "disabled";
+ };
+
sata: sata@181000 {
compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
reg-names = "ahci", "top-ctrl";
diff --git a/arch/mips/boot/dts/brcm/bcm7435.dtsi b/arch/mips/boot/dts/brcm/bcm7435.dtsi
index 2b28d91..a364896 100644
--- a/arch/mips/boot/dts/brcm/bcm7435.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7435.dtsi
@@ -386,6 +386,26 @@
status = "disabled";
};
+ hif_l2_intc: interrupt-controller@41b000 {
+ compatible = "brcm,l2-intc";
+ reg = <0x41b000 0x30>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&periph_intc>;
+ interrupts = <24>;
+ };
+
+ nand: nand@41c800 {
+ compatible = "brcm,brcmnand-v6.2", "brcm,brcmnand";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg-names = "nand", "flash-dma";
+ reg = <0x41c800 0x600>, <0x41d000 0x100>;
+ interrupt-parent = <&hif_l2_intc>;
+ interrupts = <24>, <4>;
+ status = "disabled";
+ };
+
sata: sata@181000 {
compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
reg-names = "ahci", "top-ctrl";
diff --git a/arch/mips/boot/dts/brcm/bcm97346dbsmb.dts b/arch/mips/boot/dts/brcm/bcm97346dbsmb.dts
index 27c9f12..e67eaf3 100644
--- a/arch/mips/boot/dts/brcm/bcm97346dbsmb.dts
+++ b/arch/mips/boot/dts/brcm/bcm97346dbsmb.dts
@@ -1,6 +1,7 @@
/dts-v1/;
/include/ "bcm7346.dtsi"
+/include/ "bcm97xxx-nand-cs1-bch24.dtsi"
/ {
compatible = "brcm,bcm97346dbsmb", "brcm,bcm7346";
@@ -93,6 +94,10 @@
status = "okay";
};
+&nand {
+ status = "okay";
+};
+
&sata {
status = "okay";
};
diff --git a/arch/mips/boot/dts/brcm/bcm97358svmb.dts b/arch/mips/boot/dts/brcm/bcm97358svmb.dts
index 757fe9d..ee4607f 100644
--- a/arch/mips/boot/dts/brcm/bcm97358svmb.dts
+++ b/arch/mips/boot/dts/brcm/bcm97358svmb.dts
@@ -1,6 +1,7 @@
/dts-v1/;
/include/ "bcm7358.dtsi"
+/include/ "bcm97xxx-nand-cs1-bch4.dtsi"
/ {
compatible = "brcm,bcm97358svmb", "brcm,bcm7358";
@@ -64,3 +65,7 @@
&ohci0 {
status = "okay";
};
+
+&nand {
+ status = "okay";
+};
diff --git a/arch/mips/boot/dts/brcm/bcm97362svmb.dts b/arch/mips/boot/dts/brcm/bcm97362svmb.dts
index 1b9bc4b..68fd823 100644
--- a/arch/mips/boot/dts/brcm/bcm97362svmb.dts
+++ b/arch/mips/boot/dts/brcm/bcm97362svmb.dts
@@ -1,6 +1,7 @@
/dts-v1/;
/include/ "bcm7362.dtsi"
+/include/ "bcm97xxx-nand-cs1-bch4.dtsi"
/ {
compatible = "brcm,bcm97362svmb", "brcm,bcm7362";
@@ -57,6 +58,10 @@
status = "okay";
};
+&nand {
+ status = "okay";
+};
+
&sata {
status = "okay";
};
diff --git a/arch/mips/boot/dts/brcm/bcm97425svmb.dts b/arch/mips/boot/dts/brcm/bcm97425svmb.dts
index 1c6b74d..f95ba1b 100644
--- a/arch/mips/boot/dts/brcm/bcm97425svmb.dts
+++ b/arch/mips/boot/dts/brcm/bcm97425svmb.dts
@@ -1,6 +1,7 @@
/dts-v1/;
/include/ "bcm7425.dtsi"
+/include/ "bcm97xxx-nand-cs1-bch24.dtsi"
/ {
compatible = "brcm,bcm97425svmb", "brcm,bcm7425";
@@ -95,6 +96,10 @@
status = "okay";
};
+&nand {
+ status = "okay";
+};
+
&sdhci0 {
status = "okay";
};
diff --git a/arch/mips/boot/dts/brcm/bcm97435svmb.dts b/arch/mips/boot/dts/brcm/bcm97435svmb.dts
index 64bb198..fb37b71 100644
--- a/arch/mips/boot/dts/brcm/bcm97435svmb.dts
+++ b/arch/mips/boot/dts/brcm/bcm97435svmb.dts
@@ -1,6 +1,7 @@
/dts-v1/;
/include/ "bcm7435.dtsi"
+/include/ "bcm97xxx-nand-cs1-bch24.dtsi"
/ {
compatible = "brcm,bcm97435svmb", "brcm,bcm7435";
@@ -95,6 +96,10 @@
status = "okay";
};
+&nand {
+ status = "okay";
+};
+
&sata {
status = "okay";
};
diff --git a/arch/mips/boot/dts/brcm/bcm97xxx-nand-cs1-bch24.dtsi b/arch/mips/boot/dts/brcm/bcm97xxx-nand-cs1-bch24.dtsi
new file mode 100644
index 0000000..3c24f97
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm97xxx-nand-cs1-bch24.dtsi
@@ -0,0 +1,25 @@
+&nand {
+ nandcs@1 {
+ compatible = "brcm,nandcs";
+ reg = <1>;
+ nand-on-flash-bbt;
+
+ nand-ecc-strength = <24>;
+ nand-ecc-step-size = <1024>;
+ brcm,nand-oob-sector-size = <27>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ flash1.rootfs@0 {
+ reg = <0x0 0x10000000>;
+ };
+
+ flash1.kernel@10000000 {
+ reg = <0x10000000 0x400000>;
+ };
+ };
+ };
+};
diff --git a/arch/mips/boot/dts/brcm/bcm97xxx-nand-cs1-bch4.dtsi b/arch/mips/boot/dts/brcm/bcm97xxx-nand-cs1-bch4.dtsi
new file mode 100644
index 0000000..cb53181
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm97xxx-nand-cs1-bch4.dtsi
@@ -0,0 +1,25 @@
+&nand {
+ nandcs@1 {
+ compatible = "brcm,nandcs";
+ reg = <1>;
+ nand-on-flash-bbt;
+
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ brcm,nand-oob-sector-size = <16>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ flash1.rootfs@0 {
+ reg = <0x0 0x10000000>;
+ };
+
+ flash1.kernel@10000000 {
+ reg = <0x10000000 0x400000>;
+ };
+ };
+ };
+};
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