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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2009-06-22 14:31:57 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-06-22 14:31:57 +0100
commit915166d96f5cab90b6f39f37da1139e5eab516b2 (patch)
treed5746250f994bad7c32c2853e1cc89c9181e1c88 /arch
parent3eadd3b21cec340dacdc24dd1f9735344290ca62 (diff)
parent49fb88af23f3344ba53d6dbe34ac0b1426d81006 (diff)
downloadop-kernel-dev-915166d96f5cab90b6f39f37da1139e5eab516b2.zip
op-kernel-dev-915166d96f5cab90b6f39f37da1139e5eab516b2.tar.gz
Merge branch 'next-s3c' of git://aeryn.fluff.org.uk/bjdooks/linux into devel
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/plat-s3c/gpio-config.c2
-rw-r--r--arch/arm/plat-s3c64xx/clock.c2
-rw-r--r--arch/arm/plat-s3c64xx/gpiolib.c6
-rw-r--r--arch/arm/plat-s3c64xx/include/plat/regs-clock.h10
4 files changed, 13 insertions, 7 deletions
diff --git a/arch/arm/plat-s3c/gpio-config.c b/arch/arm/plat-s3c/gpio-config.c
index 08044de..456969b 100644
--- a/arch/arm/plat-s3c/gpio-config.c
+++ b/arch/arm/plat-s3c/gpio-config.c
@@ -119,7 +119,7 @@ int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
unsigned int shift = (off & 7) * 4;
u32 con;
- if (off < 8 && chip->chip.ngpio >= 8)
+ if (off < 8 && chip->chip.ngpio > 8)
reg -= 4;
if (s3c_gpio_is_cfg_special(cfg)) {
diff --git a/arch/arm/plat-s3c64xx/clock.c b/arch/arm/plat-s3c64xx/clock.c
index 0bc2fa1..7a36e89 100644
--- a/arch/arm/plat-s3c64xx/clock.c
+++ b/arch/arm/plat-s3c64xx/clock.c
@@ -191,7 +191,7 @@ static struct clk init_clocks[] = {
.id = -1,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
- .ctrlbit = S3C_CLKCON_SCLK_UHOST,
+ .ctrlbit = S3C_CLKCON_HCLK_UHOST,
}, {
.name = "hsmmc",
.id = 0,
diff --git a/arch/arm/plat-s3c64xx/gpiolib.c b/arch/arm/plat-s3c64xx/gpiolib.c
index da7b60e..9285929 100644
--- a/arch/arm/plat-s3c64xx/gpiolib.c
+++ b/arch/arm/plat-s3c64xx/gpiolib.c
@@ -321,6 +321,11 @@ static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = {
.get_pull = s3c_gpio_getpull_updown,
};
+int s3c64xx_gpio2int_gpn(struct gpio_chip *chip, unsigned pin)
+{
+ return IRQ_EINT(0) + pin;
+}
+
static struct s3c_gpio_chip gpio_2bit[] = {
{
.base = S3C64XX_GPF_BASE,
@@ -353,6 +358,7 @@ static struct s3c_gpio_chip gpio_2bit[] = {
.base = S3C64XX_GPN(0),
.ngpio = S3C64XX_GPIO_N_NR,
.label = "GPN",
+ .to_irq = s3c64xx_gpio2int_gpn,
},
}, {
.base = S3C64XX_GPO_BASE,
diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
index 52836d4..a8777a75 100644
--- a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
+++ b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
@@ -88,11 +88,11 @@
#define S3C6400_CLKDIV2_SPI0_SHIFT (0)
/* HCLK GATE Registers */
-#define S3C_CLKCON_HCLK_BUS (1<<30)
-#define S3C_CLKCON_HCLK_SECUR (1<<29)
-#define S3C_CLKCON_HCLK_SDMA1 (1<<28)
-#define S3C_CLKCON_HCLK_SDMA2 (1<<27)
-#define S3C_CLKCON_HCLK_UHOST (1<<26)
+#define S3C_CLKCON_HCLK_3DSE (1<<31)
+#define S3C_CLKCON_HCLK_UHOST (1<<29)
+#define S3C_CLKCON_HCLK_SECUR (1<<28)
+#define S3C_CLKCON_HCLK_SDMA1 (1<<27)
+#define S3C_CLKCON_HCLK_SDMA0 (1<<26)
#define S3C_CLKCON_HCLK_IROM (1<<25)
#define S3C_CLKCON_HCLK_DDR1 (1<<24)
#define S3C_CLKCON_HCLK_DDR0 (1<<23)
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