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authorMagnus Damm <damm@opensource.se>2011-01-20 08:11:11 +0000
committerPaul Mundt <lethal@linux-sh.org>2011-01-20 21:34:31 +0900
commit71fc5099ed50d3699ba003042a721a0bf105369d (patch)
tree29a7068bc47276e0fb3476870c39b79c47f73ee7 /arch
parent2150dace47258722c67f297509bc6171e7b486ad (diff)
downloadop-kernel-dev-71fc5099ed50d3699ba003042a721a0bf105369d.zip
op-kernel-dev-71fc5099ed50d3699ba003042a721a0bf105369d.tar.gz
ARM: mach-shmobile: sh73a0 CPGA fix for PLL CFG bit
PLL1 and PLL2 in the sh73a0 CPGA has a CFG bit that must be taken into account to correctly calculate the frequency. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-shmobile/clock-sh73a0.c10
1 files changed, 9 insertions, 1 deletions
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 08fb878..bcaf58a 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -118,8 +118,16 @@ static unsigned long pll_recalc(struct clk *clk)
{
unsigned long mult = 1;
- if (__raw_readl(PLLECR) & (1 << clk->enable_bit))
+ if (__raw_readl(PLLECR) & (1 << clk->enable_bit)) {
mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1);
+ /* handle CFG bit for PLL1 and PLL2 */
+ switch (clk->enable_bit) {
+ case 1:
+ case 2:
+ if (__raw_readl(clk->enable_reg) & (1 << 20))
+ mult *= 2;
+ }
+ }
return clk->parent->rate * mult;
}
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