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authorLinus Walleij <linus.walleij@linaro.org>2014-10-14 15:05:57 +0200
committerLinus Walleij <linus.walleij@linaro.org>2016-02-11 15:52:44 +0100
commit5c3f5edbe0a1dff3f0b74f586f18f11e5c310f3c (patch)
treeb091dbfce1a881492ec082dee3eb3e7faba85561 /arch
parent92e963f50fc74041b5e9e744c330dca48e04f08d (diff)
downloadop-kernel-dev-5c3f5edbe0a1dff3f0b74f586f18f11e5c310f3c.zip
op-kernel-dev-5c3f5edbe0a1dff3f0b74f586f18f11e5c310f3c.tar.gz
ARM: realview: add flash devices to the PB1176 DTS
This adds the flash memories and ROM to the PB1175 DTS file. The secure flash is marked as "disabled" by default so as to protect the user from overwriting the boot monitor. Cc: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/dts/arm-realview-pb1176.dts32
1 files changed, 32 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/arm-realview-pb1176.dts b/arch/arm/boot/dts/arm-realview-pb1176.dts
index 1bc64cd..b7d727e 100644
--- a/arch/arm/boot/dts/arm-realview-pb1176.dts
+++ b/arch/arm/boot/dts/arm-realview-pb1176.dts
@@ -106,6 +106,31 @@
clock-frequency = <0>;
};
+ flash@30000000 {
+ compatible = "arm,versatile-flash", "cfi-flash";
+ reg = <0x30000000 0x4000000>;
+ bank-width = <4>;
+ };
+
+ fpga_flash@38000000 {
+ compatible = "arm,versatile-flash", "cfi-flash";
+ reg = <0x38000000 0x800000>;
+ bank-width = <4>;
+ };
+
+ /*
+ * The "secure flash" contains things like the boot
+ * monitor so we don't want people to accidentally
+ * screw this up. Mark the device tree node disabled
+ * by default.
+ */
+ secflash@3c000000 {
+ compatible = "arm,versatile-flash", "cfi-flash";
+ reg = <0x3c000000 0x4000000>;
+ bank-width = <4>;
+ status = "disabled";
+ };
+
soc {
#address-cells = <1>;
#size-cells = <1>;
@@ -297,6 +322,13 @@
clocks = <&uartclk>, <&pclk>;
clock-names = "uartclk", "apb_pclk";
};
+
+ /* Direct-mapped development chip ROM */
+ pb1176_rom@10200000 {
+ compatible = "direct-mapped";
+ reg = <0x10200000 0x4000>;
+ bank-width = <1>;
+ };
};
/* These peripherals are inside the FPGA rather than the DevChip */
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