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authorKevin Hilman <khilman@mvista.com>2008-01-16 21:56:14 -0800
committerTony Lindgren <tony@atomide.com>2008-03-20 16:57:54 +0200
commit4de8c75b00181db8169438e9fa4fb7bdf0db72d5 (patch)
tree80d44f8f761f6d093eaa3d2f8fcff6db45d81d66 /arch
parent06cad098d28e02d2ee3ed587bb261377e4ae2f17 (diff)
downloadop-kernel-dev-4de8c75b00181db8169438e9fa4fb7bdf0db72d5.zip
op-kernel-dev-4de8c75b00181db8169438e9fa4fb7bdf0db72d5.tar.gz
ARM: OMAP: Fix GPIO IRQ unmask
GPIO IRQ unmask doesn't actually do anything useful. The problem is hidden by a separate explicit mass unmask at the end of the chained bank handler. Signed-off-by: Kevin Hilman <khilman@mvista.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/plat-omap/gpio.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 66a1455..8c78e4e 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -1134,10 +1134,9 @@ static void gpio_mask_irq(unsigned int irq)
static void gpio_unmask_irq(unsigned int irq)
{
unsigned int gpio = irq - IH_GPIO_BASE;
- unsigned int gpio_idx = get_gpio_index(gpio);
struct gpio_bank *bank = get_irq_chip_data(irq);
- _set_gpio_irqenable(bank, gpio_idx, 1);
+ _set_gpio_irqenable(bank, gpio, 1);
}
static struct irq_chip gpio_irq_chip = {
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