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author | Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | 2013-04-09 23:06:38 +0200 |
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committer | Jason Cooper <jason@lakedaemon.net> | 2013-04-15 14:53:46 +0000 |
commit | 3b723ae8c68af92977ac16144559e0ba884a35c2 (patch) | |
tree | d84df32f0d2e4d61d6e2c88ee62787f01cbfd3a0 /arch | |
parent | 488d1a6ff9187319b55b0f886203b0410ffa2f5b (diff) | |
download | op-kernel-dev-3b723ae8c68af92977ac16144559e0ba884a35c2.zip op-kernel-dev-3b723ae8c68af92977ac16144559e0ba884a35c2.tar.gz |
arm: mvebu: PCIe Device Tree informations for Armada 370 DB
The Marvell evaluation board (DB) for the Armada 370 SoC has 2
physical full-size PCIe slots, so we enable the corresponding PCIe
interfaces in the Device Tree.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/boot/dts/armada-370-db.dts | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts index e34b280..6403acd 100644 --- a/arch/arm/boot/dts/armada-370-db.dts +++ b/arch/arm/boot/dts/armada-370-db.dts @@ -94,5 +94,22 @@ spi-max-frequency = <50000000>; }; }; + + pcie-controller { + status = "okay"; + /* + * The two PCIe units are accessible through + * both standard PCIe slots and mini-PCIe + * slots on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; + }; }; }; |