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authorThomas Gleixner <tglx@linutronix.de>2011-02-06 17:29:02 +0100
committerThomas Gleixner <tglx@linutronix.de>2011-03-24 20:35:55 +0100
commit3972f6917d05b4350c9b5ab2aaa623cd52fa4bc9 (patch)
tree3f50e01d2eff66e8ef3ab03e632609fa7105122b /arch
parent7776e233ef32d9e8152dbb31328367c65288abcf (diff)
downloadop-kernel-dev-3972f6917d05b4350c9b5ab2aaa623cd52fa4bc9.zip
op-kernel-dev-3972f6917d05b4350c9b5ab2aaa623cd52fa4bc9.tar.gz
avr32: At32ap: Convert intc irq_chip to new functions
Also replace the open coded handler call with the proper wrapper. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com> LKML-Reference: <20110206163009.096308633@linutronix.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/avr32/mach-at32ap/intc.c12
1 files changed, 5 insertions, 7 deletions
diff --git a/arch/avr32/mach-at32ap/intc.c b/arch/avr32/mach-at32ap/intc.c
index 994c4545..d9270d6 100644
--- a/arch/avr32/mach-at32ap/intc.c
+++ b/arch/avr32/mach-at32ap/intc.c
@@ -34,12 +34,12 @@ extern struct platform_device at32_intc0_device;
* TODO: We may be able to implement mask/unmask by setting IxM flags
* in the status register.
*/
-static void intc_mask_irq(unsigned int irq)
+static void intc_mask_irq(struct irq_data *d)
{
}
-static void intc_unmask_irq(unsigned int irq)
+static void intc_unmask_irq(struct irq_data *d)
{
}
@@ -47,8 +47,8 @@ static void intc_unmask_irq(unsigned int irq)
static struct intc intc0 = {
.chip = {
.name = "intc",
- .mask = intc_mask_irq,
- .unmask = intc_unmask_irq,
+ .irq_mask = intc_mask_irq,
+ .irq_unmask = intc_unmask_irq,
},
};
@@ -57,7 +57,6 @@ static struct intc intc0 = {
*/
asmlinkage void do_IRQ(int level, struct pt_regs *regs)
{
- struct irq_desc *desc;
struct pt_regs *old_regs;
unsigned int irq;
unsigned long status_reg;
@@ -69,8 +68,7 @@ asmlinkage void do_IRQ(int level, struct pt_regs *regs)
irq_enter();
irq = intc_readl(&intc0, INTCAUSE0 - 4 * level);
- desc = irq_desc + irq;
- desc->handle_irq(irq, desc);
+ generic_handle_irq(irq);
/*
* Clear all interrupt level masks so that we may handle
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