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| author | Paweł Jarosz <paweljarosz3691@gmail.com> | 2016-10-14 14:16:54 +0200 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2016-10-21 15:42:53 +0200 |
| commit | 305b54750d6bd4f36535b6b80c6f5bd6fb519e40 (patch) | |
| tree | 9ad9dc72adc7a6e05f92b2475690cc629ee05e6e /arch | |
| parent | 30522550d029f77c349f550375a70dbdc9ab7ca9 (diff) | |
| download | op-kernel-dev-305b54750d6bd4f36535b6b80c6f5bd6fb519e40.zip op-kernel-dev-305b54750d6bd4f36535b6b80c6f5bd6fb519e40.tar.gz | |
ARM: dts: rockchip: initialize rk3066 PLL clock rate
Initialize PLL, cpu bus and peripherial bus rate while kernel init.
No other module does than.
This gives us performance boost observable for example in mmc transfers.
Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/rk3066a.dtsi | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index b8c83d8..f3a5109 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -151,6 +151,14 @@ #clock-cells = <1>; #reset-cells = <1>; + assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>, + <&cru ACLK_CPU>, <&cru HCLK_CPU>, + <&cru PCLK_CPU>, <&cru ACLK_PERI>, + <&cru HCLK_PERI>, <&cru PCLK_PERI>; + assigned-clock-rates = <400000000>, <594000000>, + <300000000>, <150000000>, + <75000000>, <300000000>, + <150000000>, <75000000>; }; timer@2000e000 { |
